Matthieu Arzel

Orcid: 0000-0002-8774-7662

According to our database1, Matthieu Arzel authored at least 53 papers between 2005 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
FLoCoRA: Federated learning compression with low-rank adaptation.
CoRR, 2024

PEFSL: A deployment Pipeline for Embedded Few-Shot Learning on a FPGA SoC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023
Federated learning compression designed for lightweight communications.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

Pipelined Architecture for a Semantic Segmentation Neural Network on FPGA.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

2022
Rethinking Weight Decay for Efficient Neural Network Pruning.
J. Imaging, 2022

Energy Consumption Analysis of Pruned Semantic Segmentation Networks on an Embedded GPU.
Proceedings of the Advances in System-Integrated Intelligence, 2022

Leveraging Structured Pruning of Convolutional Neural Networks.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2022

DWT Collusion Resistant Video Watermarking Using Tardos Family Codes.
Proceedings of the 5th IEEE International Conference on Image Processing Applications and Systems, 2022

2021
Shuffled Decoding of Serial Concatenated Convolutional Codes.
Proceedings of the 11th International Symposium on Topics in Coding, 2021

Traiter et transmettre l'information à haut débit, à énergie réduite, avec flexibilité : le grand écart dans trois directions.
, 2021

2020
Continuous Pruning of Deep Convolutional Networks Using Selective Weight Decay.
CoRR, 2020

Quantized Guided Pruning for Efficient Hardware Implementations of Deep Neural Networks.
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020

2019
Budget Restricted Incremental Learning with Pre-Trained Convolutional Neural Networks and Binary Associative Memories.
J. Signal Process. Syst., 2019

A Fully Flexible Circuit Implementation of Clique-Based Neural Networks in 65-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Efficient Hardware Implementation of Incremental Learning and Inference on Chip.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019

2018
Quantized Guided Pruning for Efficient Hardware Implementations of Convolutional Neural Networks.
CoRR, 2018

Transfer Incremental Learning using Data Augmentation.
CoRR, 2018

40 Gop/s/mm<sup>2</sup> fixed-point operators for Brain Computer Interface in 65 nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
A Scaling-Less Newton-Raphson Pipelined Implementation for a Fixed-Point Reciprocal Operator.
IEEE Signal Process. Lett., 2017

A scaling-less Newton-Raphson pipelined implementation for a fixed-point inverse square root operator.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

An ultra-low power iterative clique-based neural network integrated in 65-nm CMOS.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

A 65-nm CMOS 7fJ per synaptic event clique-based neural network in scalable architecture.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Incremental learning on chip.
Proceedings of the 2017 IEEE Global Conference on Signal and Information Processing, 2017

A sub-nJ CMOS ECG classifier for wireless smart sensor.
Proceedings of the 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2017

Open-source flexible packet parser for high data rate agile network probe.
Proceedings of the 2017 IEEE Conference on Communications and Network Security, 2017

Combining FPGAs and processors for high-throughput forensics IEEE CNS 17 poster.
Proceedings of the 2017 IEEE Conference on Communications and Network Security, 2017

2016
Ultra-Low-Energy Mixed-Signal IC Implementing Encoded Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Low-Complexity Soft Detection of QAM Demapper for a MIMO System.
IEEE Commun. Lett., 2016

Toward sub-pJ per classification in Body Area Sensor Networks.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

AutoReloc: Automated Design Flow for Bitstream Relocation on Xilinx FPGAs.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

Ouessant: Flexible integration of dedicated coprocessors in Systems on Chip.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Design of analog subthreshold Encoded Neural Network circuit in sub-100nm CMOS.
Proceedings of the 2015 International Joint Conference on Neural Networks, 2015

2014
Soft Error Detection and Correction Technique for Radiation Hardening Based on C-element and BICS.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

High-speed flow-based classification on FPGA.
Int. J. Netw. Manag., 2014

Symbol-based BP detection for MIMO systems associated with non-binary LDPC codes.
Proceedings of the IEEE Wireless Communications and Networking Conference, 2014

Low-complexity LDPC-coded iterative MIMO receiver based on belief propagation algorithm for detection.
Proceedings of the 8th International Symposium on Turbo Codes and Iterative Information Processing, 2014

Low-complexity layered BP-based detection and decoding for a NB-LDPC coded MIMO system.
Proceedings of the IEEE International Conference on Communications, 2014

2013
PAPR reduction using contiguous-tone Tone Reservation technique in optical OFDM IMDD transmissions.
Proceedings of the 2013 Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC), 2013

Analog encoded neural network for power management in MPSoC.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Study of a cosmic ray impact on combinatorial logic circuits of an 8bit SAR ADC in 65nm CMOS technology.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Analog implementation of encoded neural networks.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Flexible, extensible, open-source and affordable FPGA-based traffic generator.
Proceedings of the first edition workshop on High performance and programmable networking, 2013

2012
Stochastic chase decoder for reed-solomon codes.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012

Hardware acceleration of SVM-based traffic classification on FPGA.
Proceedings of the 8th International Wireless Communications and Mobile Computing Conference, 2012

Adapted scheduling of QC-LDPC decoding for multistandard receivers.
Proceedings of the 7th International Symposium on Turbo Codes and Iterative Information Processing, 2012

Multi-standard trellis-based FEC decoder.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

2011
Stochastic Multiple Stream Decoding of Cortex Codes.
IEEE Trans. Signal Process., 2011

A Self-Powered Telemetry System to Estimate the Postoperative Instability of a Knee Implant.
IEEE Trans. Biomed. Eng., 2011

2010
Stochastic Decoding of Turbo Codes.
IEEE Trans. Signal Process., 2010

2009
Analog Decoder Performance Degradation Due to BJTs' Parasitic Elements.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

2007
Semi-Iterative Analog Turbo Decoding.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

2006
Semi-iterative analog turbo decoding.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
. Analog slice turbo decoding.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005


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