Matthias Sauer

Proceedings of the IEEE International Test Conference, 2019

On Integrating Lightweight Encryption in Reconfigurable Scan Networks.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE European Test Symposium, 2019

On Secure Data Flow in Reconfigurable Scan Networks.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018

Efficient generation of parametric test conditions for AMS chips with an interval constraint solver.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Detecting and Resolving Security Violations in Reconfigurable Scan Networks.

[BibT_eX]

[DOI]

Pascal Raiola

Michael A. Kochte

Ahmed Atteya

Laura Rodríguez Gómez

Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Towards the formal verification of security properties of a Network-on-Chip router.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE European Test Symposium, 2018

Online prevention of security violations in reconfigurable scan networks.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE European Test Symposium, 2018

2017

Specification and verification of security in reconfigurable scan networks.

[BibT_eX]

[DOI]

Michael A. Kochte

Laura Rodríguez Gómez

Pascal Raiola

Proceedings of the 22nd IEEE European Test Symposium, 2017

Sensitized path PUF: A lightweight embedded physical unclonable function.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016

A Flexible Framework for the Automatic Generation of SBST Programs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Systemic Frequency Biases in Ring Oscillator PUFs on FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Multi Scale Comput. Syst., 2016

PHAETON: A SAT-Based Framework for Timing-Aware Path Sensitization.

[BibT_eX]

[DOI]

Ilia Polian

IEEE Trans. Computers, 2016

On Metrics to Quantify the Inter-Device Uniqueness of PUFs.

[BibT_eX]

[DOI]

Linus Feiten

IACR Cryptol. ePrint Arch., 2016

Extracting the RC4 secret key of the Open Smart Grid Protocol.

[BibT_eX]

[DOI]

Linus Feiten

IACR Cryptol. ePrint Arch., 2016

Effective generation and evaluation of diagnostic SBST programs.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

SAT-Based Combinational and Sequential Dependency Computation.

[BibT_eX]

[DOI]

Proceedings of the Hardware and Software: Verification and Testing, 2016

Formal verification of secure reconfigurable scan network infrastructure.

[BibT_eX]

[DOI]

Proceedings of the 21th IEEE European Test Symposium, 2016

On Optimal Power-Aware Path Sensitization.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE Asian Test Symposium, 2016

Mixed 01X-RSL-Encoding for fast and accurate ATPG with unknowns.

[BibT_eX]

[DOI]

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

Formal Vulnerability Analysis of Security Components.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Accurate QBF-Based Test Pattern Generation in Presence of Unknown Values.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Improving diagnosis resolution of a fault detection test set.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Multi-cycle Circuit Parameter Independent ATPG for interconnect open defects.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Modeling Unknown Values in Test and Verification.

[BibT_eX]

[DOI]

Proceedings of the Formal Modeling and Verification of Cyber-Physical Systems, 2015

Identification of high power consuming areas with gate type and logic level information.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE European Test Symposium, 2015

Improving RO-PUF quality on FPGAs by incorporating design-dependent frequency biases.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE European Test Symposium, 2015

On the automatic generation of SBST test programs for in-field test.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Solving DQBF through quantifier elimination.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

Testing time - time to test?: using formal methods for the timing analysis of digital circuits.

[BibT_eX]

[DOI]

PhD thesis, 2014

Exact Logic and Fault Simulation in Presence of Unknowns.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2014

QBF with Soft Variables.

[BibT_eX]

[DOI]

Electron. Commun. Eur. Assoc. Softw. Sci. Technol., 2014

Efficient SAT-Based Circuit Initialization for Larger Designs.

[BibT_eX]

[DOI]

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

Test pattern generation in presence of unknown values based on restricted symbolic logic.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Test Conference, 2014

Variation-aware deterministic ATPG.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE European Test Symposium, 2014

Recent advances in SAT-based ATPG: Non-standard fault models, multi constraints and optimization.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

An effective approach to automatic functional processor test generation for small-delay faults.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Using MaxBMC for Pareto-optimal circuit initialization.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Efficient SMT-based ATPG for interconnect open defects.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

A Formal Approach to the Traveling Professor Problem.

[BibT_eX]

Stefan Kupferschmid

Proceedings of the Aspekte der Technischen Informatik, 2014

Incremental Encoding and Solving of Cardinality Constraints.

[BibT_eX]

[DOI]

Proceedings of the Automated Technology for Verification and Analysis, 2014

Circuit Parameter Independent Test Pattern Generation for Interconnect Open Defects.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013

Implementation and Analysis of Ring Oscillator PUFs on 60 nm Altera Cyclone FPGAs.

[BibT_eX]

[DOI]

Inf. Secur. J. A Glob. Perspect., 2013

SAT-Based Analysis of Sensitizable Paths.

[BibT_eX]

[DOI]

IEEE Des. Test, 2013

Identification of critical variables using an FPGA-based fault injection framework.

[BibT_eX]

[DOI]

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Equivalence Checking for Partial Implementations Revisited.

[BibT_eX]

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013

Accurate Computation of Sensitizable Paths Using Answer Set Programming.

[BibT_eX]

[DOI]

Proceedings of the Logic Programming and Nonmonotonic Reasoning, 2013

Early-life-failure detection using SAT-based ATPG.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Test Conference, 2013

Equivalence checking of partial designs using dependency quantified Boolean formulae.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Detection of early-life failures in high-K metal-gate transistors and ultra low-K inter-metal dielectrics.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

Search Space Reduction for Low-Power Test Generation.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asian Test Symposium, 2013

Accurate Multi-cycle ATPG in Presence of X-Values.

[BibT_eX]

[DOI]

Dominik Erb

Michael A. Kochte

Proceedings of the 22nd Asian Test Symposium, 2013

Provably optimal test cube generation using quantified boolean formula solving.

[BibT_eX]

[DOI]

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

SAT-ATPG using preferences for improved detection of complex defect mechanisms.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Analysis of Reachable Sensitisable Paths in Sequential Circuits with SAT and Craig Interpolation.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on VLSI Design, 2012

Functional test of small-delay faults using SAT and Craig interpolation.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Test Conference, 2012

Small-delay-fault ATPG with waveform accuracy.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

On the quality of test vectors for post-silicon characterization.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE European Test Symposium, 2012

Multi-conditional SAT-ATPG for power-droop testing.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE European Test Symposium, 2012

#SAT-based vulnerability analysis of security components - A case study.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

On the optimality of K longest path generation algorithm under memory constraints.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Variation-Aware Fault Grading.

[BibT_eX]

[DOI]