Matthias Jung

Alex Orailoglu

Int. J. Parallel Program., 2022

A Weighted Current Summation Based Mixed Signal DRAM-PIM Architecture for Deep Neural Network Inference.

[BibT_eX]

[DOI]

Mohammad Hassani Sadi

Andre Guntoro

IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

Split'n'Cover: ISO 26262 Hardware Safety Analysis with SystemC.

[BibT_eX]

[DOI]

Denis Uecker

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2022

A Framework for Formal Verification of DRAM Controllers.

[BibT_eX]

[DOI]

Proceedings of the 2022 International Symposium on Memory Systems, 2022

Unveiling the Real Performance of LPDDR5 Memories.

[BibT_eX]

[DOI]

Proceedings of the 2022 International Symposium on Memory Systems, 2022

2021

A Novel DRAM Architecture for Improved Bandwidth Utilization and Latency Reduction Using Dual-Page Operation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2021

SEC-Learn: Sensor Edge Cloud for Federated Learning - Invited Paper.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2021

Online Working Set Change Detection with Constant Complexity: The Cornerstone for Memory Management Algorithms in Scalable Systems.

[BibT_eX]

[DOI]

Proceedings of the MEMSYS 2021: The International Symposium on Memory Systems, Washington, USA, September 27, 2021

An LPDDR4 Safety Model for Automotive Applications.

[BibT_eX]

[DOI]

Proceedings of the MEMSYS 2021: The International Symposium on Memory Systems, Washington, USA, September 27, 2021

Exploration of DDR5 with the Open-Source Simulator DRAMSys.

[BibT_eX]

[DOI]

Lukas Steiner

Proceedings of the Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2021

The Dynamic Random Access Memory Challenge in Embedded Computing Systems.

[BibT_eX]

[DOI]

Daniel Rodrigues Carvalho

Proceedings of the A Journey of Embedded and Cyber-Physical Systems, 2021

A Novel DRAM-Based Process-in-Memory Architecture and its Implementation for CNNs.

[BibT_eX]

[DOI]

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

eBrainII: a 3 kW Realtime Custom 3D DRAM Integrated ASIC Implementation of a Biologically Plausible Model of a Human Scale Cortex.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2020

The gem5 Simulator: Version 20.0+.

[BibT_eX]

[DOI]

Amin Farmahini Farahani

Hamidreza Khaleghzadeh

CoRR, 2020

DRAMSys4.0: A Fast and Cycle-Accurate SystemC/TLM-Based DRAM Simulator.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2020

System simulation with PULP virtual platform and SystemC.

[BibT_eX]

[DOI]

Proceedings of the RAPIDO 2020 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2020

Efficient Generation of Application Specific Memory Controllers.

[BibT_eX]

[DOI]

Proceedings of the MEMSYS 2020: The International Symposium on Memory Systems, 2020

An Energy Efficient 3D-Heterogeneous Main Memory Architecture for Mobile Devices.

[BibT_eX]

[DOI]

Muhammad Mohsin Ghaffar

Syed Mohammad Asad Hassan Jafri

Proceedings of the MEMSYS 2020: The International Symposium on Memory Systems, 2020

A Low Power In-DRAM Architecture for Quantized CNNs using Fast Winograd Convolutions.

[BibT_eX]

[DOI]

Muhammad Mohsin Ghaffar

Proceedings of the MEMSYS 2020: The International Symposium on Memory Systems, 2020

Fast and Accurate DRAM Simulation: Can we Further Accelerate it?

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

eBrainII: A 3 kW Realtime Custom 3D DRAM integrated ASIC implementation of a Biologically Plausible Model of a Human Scale Cortex.

[BibT_eX]

[DOI]

CoRR, 2019

A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

Fast validation of DRAM protocols with timed petri nets.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Memory Systems, 2019

An In-DRAM Neural Network Processing Engine.

[BibT_eX]

[DOI]

Chirag Sudarshan

Jan Lappas

Muhammad Mohsin Ghaffar

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Rapid Identification of Shared Memory in Multithreaded Embedded Systems with Static Scheduling.

[BibT_eX]

[DOI]

Proceedings of the 48th International Conference on Parallel Processing, 2019

Speculative Temporal Decoupling Using fork().

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018

A Memory Centric Architecture of the Link Assessment Algorithm in Large Graphs.

[BibT_eX]

[DOI]

Christian Brugger

Valentin Grigorovici

Christian de Schryver

Carl Christian Rheinländer

Katharina Anna Zweig

IEEE Des. Test, 2018

BOSMI: a framework for non-intrusive monitoring and testing of embedded multithreaded software on the logical level.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

A Model-Based Safety Analysis of Dependencies Across Abstraction Layers.

[BibT_eX]

[DOI]

Leandro Avila da Silva

Proceedings of the Computer Safety, Reliability, and Security, 2018

A Framework for Non-intrusive Trace-driven Simulation of Manycore Architectures with Dynamic Tracing Configuration.

[BibT_eX]

[DOI]

Proceedings of the Runtime Verification - 18th International Conference, 2018

Efficient coding scheme for DDR4 memory subsystems.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Memory Systems, 2018

Driving into the memory wall: the role of memory for advanced driver assistance systems and autonomous driving.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Memory Systems, 2018

The Role of Memories in Transprecision Computing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Enabling Continuous Software Engineering for Embedded Systems Architectures with Virtual Prototypes.

[BibT_eX]

[DOI]

Pablo Oliveira Antonino

Proceedings of the Software Architecture, 2018

An analysis on retention error behavior and power consumption of recent DDR4 DRAMs.

[BibT_eX]

[DOI]

Deepak M. Mathew

Martin Schultheis

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Improving the error behavior of DRAM by exploiting its Z-channel property.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

A Customized Many-Core Hardware Acceleration Platform for Short Read Mapping Problems Using Distributed Memory Interface with 3D-Stacked Architecture.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2017

DRAMSpec: A High-Level DRAM Timing, Power and Area Exploration Tool.

[BibT_eX]

[DOI]

Int. J. Parallel Program., 2017

3D-Stacked Many-Core Architecture for Biological Sequence Analysis Problems.

[BibT_eX]

[DOI]

Int. J. Parallel Program., 2017

A Platform to Analyze DDR3 DRAM's Power and Retention Time.

[BibT_eX]

[DOI]

Carl Christian Rheinländer

Deepak M. Mathew

IEEE Des. Test, 2017

System simulation with gem5 and SystemC: The keystone for full interoperability.

[BibT_eX]

[DOI]

Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

Supervised testing of concurrent software in embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

A new state model for DRAMs using Petri Nets.

[BibT_eX]

[DOI]

Kira Kraft

Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

A Bank-Wise DRAM Power Model for System Simulations.

[BibT_eX]

[DOI]

Proceedings of the 9th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2017

Using run-time reverse-engineering to optimize DRAM refresh.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Memory Systems, 2017

Integrating DRAM power-down modes in gem5 and quantifying their impact.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Memory Systems, 2017

2016

A cross layer approach for efficient thermal management in 3D stacked SoCs.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2016

Exploring system performance using elastic traces: Fast, accurate and portable.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

A new bank sensitive DRAMPower model for efficient design space exploration.

[BibT_eX]

[DOI]

Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

Reverse Engineering of DRAMs: Row Hammer with Crosshair.

[BibT_eX]

[DOI]

Carl Christian Rheinländer

Proceedings of the Second International Symposium on Memory Systems, 2016

ConGen: An Application Specific DRAM Memory Controller Generator.

[BibT_eX]

[DOI]

Proceedings of the Second International Symposium on Memory Systems, 2016

Invited - Approximate computing with partially unreliable dynamic random access memory - approximate DRAM.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

Efficient reliability management in SoCs - an approximate DRAM perspective.

[BibT_eX]

[DOI]

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

DRAMSys: A Flexible DRAM Subsystem Design Space Exploration Framework.

[BibT_eX]

[DOI]

IPSJ Trans. Syst. LSI Des. Methodol., 2015

A high-level DRAM timing, power and area exploration tool.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Omitting Refresh: A Case Study for Commodity and Wide I/O DRAMs.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Symposium on Memory Systems, 2015

Thermal Aspects and High-Level Explorations of 3D Stacked DRAMs.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

A Custom Computing System for Finding Similarties in Complex Networks.

[BibT_eX]

[DOI]

Christian de Schryver

Katharina Anna Zweig