Matthias Gries

Orcid: 0000-0001-9379-1603

According to our database1, Matthias Gries authored at least 30 papers between 2000 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2015
Time Series Characterization of Gaming Workload for Runtime Power Management.
IEEE Trans. Computers, 2015

2011
A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling.
IEEE J. Solid State Circuits, 2011

SCC: A Flexible Architecture for Many-Core Platform Research.
Comput. Sci. Eng., 2011

Phase-Based Application-Driven Hierarchical Power Management on the Single-chip Cloud Computer.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010

LMS-based low-complexity game workload prediction for DVFS.
Proceedings of the 28th International Conference on Computer Design, 2010

A virtual platform environment for exploring power, thermal and reliability management control strategies in high-performance multicores.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

2009
Implementing a Software-Based 802.11 MAC on a Customized Platform.
Proceedings of the 6th IEEE Consumer Communications and Networking Conference, 2009

2008
SystemClick: a domain-specific framework for early exploration using functional performance models.
Proceedings of the 45th Design Automation Conference, 2008

2007
SystemQ: Bridging the gap between queuing-based performance evaluation and SystemC.
Des. Autom. Embed. Syst., 2007

Interactive presentation: Hard- and software modularity of the NOVA MPSoC platform.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Application-Driven Development of Concurrent Packet Processing Platforms.
Proceedings of the Fifth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2006), 2006

Performance Evaluation of Packet Processing Architectures Using Multiclass Queuing Networks.
Proceedings of the Proceedings 39th Annual Simulation Symposium (ANSS-39 2006), 2006

2005
SystemQ: A Queuing-Based Approach to Architecture Performance Evaluation with SystemC.
Proceedings of the Embedded Computer Systems: Architectures, 2005

Trends in Access Networks and their Implementation in DSLAMs.
Proceedings of the 30th Annual IEEE Conference on Local Computer Networks (LCN 2005), 2005

Modular Reference Implementation of an IP-DSLAM.
Proceedings of the 10th IEEE Symposium on Computers and Communications (ISCC 2005), 2005

Performance Evaluation of VLSI platforms using SystemQ.
Proceedings of the 35. Jahrestagung der Gesellschaft für Informatik, 2005

Application-Driven Design of Cost-Efficient Communications Platforms.
Proceedings of the 35. Jahrestagung der Gesellschaft für Informatik, 2005

Modular domain-specific implementation and exploration framework for embedded software platforms.
Proceedings of the 42nd Design Automation Conference, 2005

2004
Methods for evaluating and covering the design space during early design development.
Integr., 2004

Developing a Flexible Interface for RapidIO, Hypertransport, and PCI-Express.
Proceedings of the 2004 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), 2004

Fast cycle-accurate simulation and instruction set generation for constraint-based descriptions of programmable architectures.
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

2003
Comparing Analytical Modeling with Simulation for Network Processors: A Case Study.
Proceedings of the 2003 Design, 2003

Programming challenges in network processor deployment.
Proceedings of the International Conference on Compilers, 2003

2002
Supporting a Low Delay Best-Effort Class in the Presence of Real-Time Traffic.
Proceedings of the 8th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2002), 2002

A framework for evaluating design tradeoffs in packet processing architectures.
Proceedings of the 39th Design Automation Conference, 2002

2001
Algorithm architecture trade offs in network processor design.
PhD thesis, 2001

FunState-an internal design representation for codesign.
IEEE Trans. Very Large Scale Integr. Syst., 2001

Embedded Software in Network Processors - Models and Algorithms.
Proceedings of the Embedded Software, First International Workshop, 2001

2000
The Impact of Recent DRAM Architectures on Embedded Systems Performance.
Proceedings of the 26th EUROMICRO 2000 Conference, 2000


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