Matthias Függer

Orcid: 0000-0001-5765-0301

According to our database1, Matthias Függer authored at least 69 papers between 2004 and 2024.

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Bibliography

2024
Faithful Dynamic Timing Analysis of Digital Circuits Using Continuous Thresholded Mode-Switched ODEs.
CoRR, 2024

Majority Consensus Thresholds in Competitive Lotka-Volterra Populations.
Proceedings of the 43rd ACM Symposium on Principles of Distributed Computing, 2024

2023
PALS: Distributed Gradient Clocking on Chip.
IEEE Trans. Very Large Scale Integr. Syst., November, 2023

Continuity of Thresholded Mode-Switched ODEs and Digital Circuit Delay Models.
Proceedings of the 26th ACM International Conference on Hybrid Systems: Computation and Control, 2023

On the Susceptibility of QDI Circuits to Transient Faults.
Proceedings of the Formal Modeling and Analysis of Timed Systems, 2023

A Hybrid Delay Model for Interconnected Multi-Input Gates.
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023

2022
Fast All-Digital Clock Frequency Adaptation Circuit for Voltage Droop Tolerance.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Distributed computation with continual population growth.
Distributed Comput., 2022

MobsPy: A Meta-species Language for Chemical Reaction Networks.
Proceedings of the Computational Methods in Systems Biology, 2022

On Specifications and Proofs of Timed Circuits.
Proceedings of the Principles of Systems Design, 2022

Computing at the border of abstractions: the power of timed, non-binary, distributed circuits. (Le calcul à la frontière des abstractions : la puissance des circuits temporisés, non binaires, distribués).
, 2022

2021
Tight Bounds for Asymptotic and Approximate Consensus.
J. ACM, 2021

The Involution Tool for Accurate Digital Timing and Power Analysis.
Integr., 2021

Reaching Agreement in Competitive Microbial Systems.
CoRR, 2021

A Composable Glitch-Aware Delay Model.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

2020
Synchronizer-Free Digital Link Controller.
IEEE Trans. Circuits Syst., 2020

A Faithful Binary Circuit Model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

On the radius of nonsplit graphs and information dissemination in dynamic networks.
Discret. Appl. Math., 2020

Synthesis in Presence of Dynamic Links.
Proceedings of the Proceedings 11th International Symposium on Games, 2020

PALS: Plesiochronous and Locally Synchronous Systems.
Proceedings of the 26th IEEE International Symposium on Asynchronous Circuits and Systems, 2020

2019
The Involution Tool for Accurate Digital Timingand Power Analysis.
Proceedings of the 29th International Symposium on Power and Timing Modeling, 2019

Transistor-Level Analysis of Dynamic Delay Models.
Proceedings of the 25th IEEE International Symposium on Asynchronous Circuits and Systems, 2019

2018
Metastability-Containing Circuits.
IEEE Trans. Computers, 2018

Fast Multidimensional Asymptotic and Approximate Consensus.
Proceedings of the 32nd International Symposium on Distributed Computing, 2018

A faithful binary circuit model with adversarial noise.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
New transience bounds for max-plus linear systems.
Discret. Appl. Math., 2017

Lower Bounds for Asymptotic Consensus in Dynamic Networks.
CoRR, 2017

Brief Announcement: Lower Bounds for Asymptotic Consensus in Dynamic Networks.
Proceedings of the 31st International Symposium on Distributed Computing, 2017

Metastability Tolerant Computing.
Proceedings of the 23rd IEEE International Symposium on Asynchronous Circuits and Systems, 2017

Metastability-Aware Memory-Efficient Time-to-Digital Converters.
Proceedings of the 23rd IEEE International Symposium on Asynchronous Circuits and Systems, 2017

2016
Unfaithful Glitch Propagation in Existing Binary Circuit Models.
IEEE Trans. Computers, 2016

HEX: Scaling honeycombs is easier than scaling clock trees.
J. Comput. Syst. Sci., 2016

Multidimensional Asymptotic Consensus in Dynamic Networks.
CoRR, 2016

Fast, Robust, Quantizable Approximate Consensus.
Proceedings of the 43rd International Colloquium on Automata, Languages, and Programming, 2016

2015
Time Complexity of Link Reversal Routing.
ACM Trans. Algorithms, 2015

The effect of forgetting on the performance of a synchronizer.
Perform. Evaluation, 2015

Fault-tolerant Distributed Systems in Hardware.
Bull. EATCS, 2015

Amortized Averaging Algorithms for Approximate Consensus.
CoRR, 2015

A Proof of the Convergence of the Hegselmann-Krause Dynamics on the Circle.
CoRR, 2015

Approximate Consensus in Highly Dynamic Networks: The Role of Averaging Algorithms.
Proceedings of the Automata, Languages, and Programming - 42nd International Colloquium, 2015

Experimental Validation of a Faithful Binary Circuit Model.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Towards binary circuit models that faithfully capture physical solvability.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Diffusive clock synchronization in highly dynamic networks.
Proceedings of the 49th Annual Conference on Information Sciences and Systems, 2015

2014
Rigorously modeling self-stabilizing fault-tolerant circuits: An ultra-robust clocking scheme for systems-on-chip.
J. Comput. Syst. Sci., 2014

Fault-tolerant algorithms for tick-generation in asynchronous logic: Robust pulse generation.
J. ACM, 2014

Runtime verification of embedded real-time systems.
Formal Methods Syst. Des., 2014

Faithful Glitch Propagation in Binary Circuit Models.
CoRR, 2014

Approximate Consensus in Highly Dynamic Networks.
CoRR, 2014

2013
On the performance of a retransmission-based synchronizer.
Theor. Comput. Sci., 2013

Transience Bounds for Distributed Algorithms.
Proceedings of the Formal Modeling and Analysis of Timed Systems, 2013

Efficient Construction of Global Time in SoCs Despite Arbitrary Faults.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012
Reconciling fault-tolerant distributed computing and systems-on-chip.
Distributed Comput., 2012

New Transience Bounds for Long Walks
CoRR, 2012

FATAL+: A Self-Stabilizing Byzantine Fault-tolerant Clocking Scheme for SoCs
CoRR, 2012

Brief Announcement: The Degrading Effect of Forgetting on a Synchronizer.
Proceedings of the Stabilization, Safety, and Security of Distributed Systems, 2012

Real-Time Runtime Verification on Chip.
Proceedings of the Runtime Verification, Third International Conference, 2012

Efficient Checking of Link-Reversal-Based Concurrent Systems.
Proceedings of the CONCUR 2012 - Concurrency Theory - 23rd International Conference, 2012

2011
On the Transience of Linear Max-Plus Dynamical Systems
CoRR, 2011

Fault-Tolerant Algorithms for Tick-Generation in Asynchronous Logic: Robust Pulse Generation - [Extended Abstract].
Proceedings of the Stabilization, Safety, and Security of Distributed Systems, 2011

Brief announcement: full reversal routing as a linear dynamical system.
Proceedings of the SPAA 2011: Proceedings of the 23rd Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2011

Partial is Full.
Proceedings of the Structural Information and Communication Complexity, 2011

Full Reversal Routing as a Linear Dynamical System.
Proceedings of the Structural Information and Communication Complexity, 2011

2010
How to Speed-Up Fault-Tolerant Clock Generation in VLSI Systems-on-Chip via Pipelining.
Proceedings of the Eighth European Dependable Computing Conference, 2010

2009
Safely Stimulating the Clock Synchronization Algorithm in Time-Triggered Systems - a Combined Formal & Experimental Approach.
IEEE Trans. Ind. Informatics, 2009

Brief announcement: how to speed-up fault-tolerant clock generation in VLSI systems-on-chip via pipelining.
Proceedings of the 28th Annual ACM Symposium on Principles of Distributed Computing, 2009

On the Threat of Metastability in an Asynchronous Fault-Tolerant Clock Generation Scheme.
Proceedings of the 15th IEEE Symposium on Asynchronous Circuits and Systems, 2009

2008
Mapping a Fault-Tolerant Distributed Algorithm to Systems on Chip.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2006
Fault-Tolerant Distributed Clock Generation in VLSI Systems-on-Chip.
Proceedings of the Sixth European Dependable Computing Conference, 2006

2004
Embedded Real-Time-Tracer - An Approach with IDE.
Proceedings of the Second Workshop on Intelligent Solutions in Embedded Systems, 2004


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