Matthias Függer
Orcid: 0000-0001-5765-0301
According to our database1,
Matthias Függer
authored at least 69 papers
between 2004 and 2024.
Collaborative distances:
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Bibliography
2024
Faithful Dynamic Timing Analysis of Digital Circuits Using Continuous Thresholded Mode-Switched ODEs.
CoRR, 2024
Proceedings of the 43rd ACM Symposium on Principles of Distributed Computing, 2024
2023
IEEE Trans. Very Large Scale Integr. Syst., November, 2023
Proceedings of the 26th ACM International Conference on Hybrid Systems: Computation and Control, 2023
Proceedings of the Formal Modeling and Analysis of Timed Systems, 2023
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023
2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Proceedings of the Computational Methods in Systems Biology, 2022
Proceedings of the Principles of Systems Design, 2022
Computing at the border of abstractions: the power of timed, non-binary, distributed circuits. (Le calcul à la frontière des abstractions : la puissance des circuits temporisés, non binaires, distribués).
, 2022
2021
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021
2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Discret. Appl. Math., 2020
Proceedings of the Proceedings 11th International Symposium on Games, 2020
Proceedings of the 26th IEEE International Symposium on Asynchronous Circuits and Systems, 2020
2019
Proceedings of the 29th International Symposium on Power and Timing Modeling, 2019
Proceedings of the 25th IEEE International Symposium on Asynchronous Circuits and Systems, 2019
2018
Proceedings of the 32nd International Symposium on Distributed Computing, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
Proceedings of the 31st International Symposium on Distributed Computing, 2017
Proceedings of the 23rd IEEE International Symposium on Asynchronous Circuits and Systems, 2017
Proceedings of the 23rd IEEE International Symposium on Asynchronous Circuits and Systems, 2017
2016
IEEE Trans. Computers, 2016
J. Comput. Syst. Sci., 2016
Proceedings of the 43rd International Colloquium on Automata, Languages, and Programming, 2016
2015
Perform. Evaluation, 2015
CoRR, 2015
Proceedings of the Automata, Languages, and Programming - 42nd International Colloquium, 2015
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 49th Annual Conference on Information Sciences and Systems, 2015
2014
Rigorously modeling self-stabilizing fault-tolerant circuits: An ultra-robust clocking scheme for systems-on-chip.
J. Comput. Syst. Sci., 2014
Fault-tolerant algorithms for tick-generation in asynchronous logic: Robust pulse generation.
J. ACM, 2014
2013
Proceedings of the Formal Modeling and Analysis of Timed Systems, 2013
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
2012
Distributed Comput., 2012
CoRR, 2012
Proceedings of the Stabilization, Safety, and Security of Distributed Systems, 2012
Proceedings of the Runtime Verification, Third International Conference, 2012
Proceedings of the CONCUR 2012 - Concurrency Theory - 23rd International Conference, 2012
2011
Fault-Tolerant Algorithms for Tick-Generation in Asynchronous Logic: Robust Pulse Generation - [Extended Abstract].
Proceedings of the Stabilization, Safety, and Security of Distributed Systems, 2011
Proceedings of the SPAA 2011: Proceedings of the 23rd Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2011
Proceedings of the Structural Information and Communication Complexity, 2011
Proceedings of the Structural Information and Communication Complexity, 2011
2010
How to Speed-Up Fault-Tolerant Clock Generation in VLSI Systems-on-Chip via Pipelining.
Proceedings of the Eighth European Dependable Computing Conference, 2010
2009
Safely Stimulating the Clock Synchronization Algorithm in Time-Triggered Systems - a Combined Formal & Experimental Approach.
IEEE Trans. Ind. Informatics, 2009
Brief announcement: how to speed-up fault-tolerant clock generation in VLSI systems-on-chip via pipelining.
Proceedings of the 28th Annual ACM Symposium on Principles of Distributed Computing, 2009
On the Threat of Metastability in an Asynchronous Fault-Tolerant Clock Generation Scheme.
Proceedings of the 15th IEEE Symposium on Asynchronous Circuits and Systems, 2009
2008
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008
2006
Proceedings of the Sixth European Dependable Computing Conference, 2006
2004
Embedded Real-Time-Tracer - An Approach with IDE.
Proceedings of the Second Workshop on Intelligent Solutions in Embedded Systems, 2004