Matthew Poremba
According to our database1,
Matthew Poremba
authored at least 19 papers
between 2010 and 2023.
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Bibliography
2023
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023
2018
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018
2017
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017
2016
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016
Fine-granularity tile-level parallelism in non-volatile memory architecture with two-dimensional bank subdivision.
Proceedings of the 53rd Annual Design Automation Conference, 2016
2015
EECache: A Comprehensive Study on the Architectural Design for Energy-Efficient Last-Level Caches in Chip Multiprocessors.
ACM Trans. Archit. Code Optim., 2015
IEEE Comput. Archit. Lett., 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Heterogeneous architecture design with emerging 3D and non-volatile memory technologies.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
EECache: exploiting design choices in energy-efficient last-level caches for chip multiprocessors.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014
NoΔ: Leveraging delta compression for end-to-end memory access in NoC based multicores.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
Proceedings of the 2014 International 3D Systems Integration Conference, 2014
A cost benefit analysis: The impact of defect clustering on the necessity of pre-bond tests.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014
2013
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013
2012
NVMain: An Architectural-Level Main Memory Simulator for Emerging Non-volatile Memories.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012
2010
Evaluation of using inductive/capacitive-coupling vertical interconnects in 3D network-on-chip.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010