Matthew M. Ziegler

According to our database, Matthew M. Ziegler authored at least 48 papers between 2001 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC.

Monodeep Kar, Joel Silberman, Swagath Venkataramani, Viji Srinivasan, Bruce M. Fleischer, Joshua Rubin, JohnDavid Lancaster, Sae Kyu Lee, Matthew Cohen, Matthew M. Ziegler, Nianzheng Cao, Sandra Woodward, Ankur Agrawal, Ching Zhou, Prasanth Chatarasi, Thomas Gooding, Michael Guillorn, Bahman Hekmatshoartabari, Philip Jacob, Radhika Jain, Shubham Jain, Jinwook Jung, Kyu-Hyoun Kim, Siyu Koswatta, Martin Lutz, Alberto Mannari, Abey Mathew, Indira Nair, Ashish Ranjan, Zhibin Ren, Scot Rider, Thomas Roewer, David L. Satterfield, Marcel Schaal, Sanchari Sen, Gustavo Tellez, Hung Tran, Wei Wang, Vidhi Zalani, Jintao Zhang, Xin Zhang, Vinay Shah, Robert M. Senger, Arvind Kumar, Pong-Fei Lu, Leland Chang

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2022

A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling.

Sae Kyu Lee, Ankur Agrawal, Joel Silberman, Matthew M. Ziegler, Mingu Kang, Swagath Venkataramani, Nianzheng Cao, Bruce M. Fleischer, Michael Guillorn, Matthew Cohen, Silvia M. Mueller, Jinwook Oh, Martin Lutz, Jinwook Jung, Siyu Koswatta, Ching Zhou, Vidhi Zalani, Monodeep Kar, James Bonanno, Robert Casatuta, Chia-Yu Chen, Jungwook Choi, Howard Haynie, Alyssa Herbert, Radhika Jain, Kyu-Hyoun Kim, Yulong Li, Zhibin Ren, Scot Rider, Marcel Schaal, Kerstin Schelm, Michael Scheuermann, Xiao Sun, Hung Tran, Naigang Wang, Wei Wang, Xin Zhang, Vinay Shah, Brian W. Curran, Vijayalakshmi Srinivasan, Pong-Fei Lu, Sunil Shukla, Kailash Gopalakrishnan, Leland Chang

IEEE J. Solid State Circuits, 2022

Design Flow Parameter Optimization with Multi-Phase Positive Nondeterministic Tuning.

Matthew M. Ziegler, Lakshmi N. Reddy, Robert L. Franch

Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

2021

A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling.

Ankur Agrawal, Sae Kyu Lee, Joel Silberman, Matthew M. Ziegler, Mingu Kang, Swagath Venkataramani, Nianzheng Cao, Bruce M. Fleischer, Michael Guillorn, Matt Cohen, Silvia M. Mueller, Jinwook Oh, Martin Lutz, Jinwook Jung, Siyu Koswatta, Ching Zhou, Vidhi Zalani, James Bonanno, Robert Casatuta, Chia-Yu Chen, Jungwook Choi, Howard Haynie, Alyssa Herbert, Radhika Jain, Monodeep Kar, Kyu-Hyoun Kim, Yulong Li, Zhibin Ren, Scot Rider, Marcel Schaal, Kerstin Schelm, Michael Scheuermann, Xiao Sun, Hung Tran, Naigang Wang, Wei Wang, Xin Zhang, Vinay Shah, Brian W. Curran, Vijayalakshmi Srinivasan, Pong-Fei Lu, Sunil Shukla, Leland Chang, Kailash Gopalakrishnan

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

RaPiD: AI Accelerator for Ultra-low Precision Training and Inference.

Swagath Venkataramani, Vijayalakshmi Srinivasan, Wei Wang, Sanchari Sen, Jintao Zhang, Ankur Agrawal, Monodeep Kar, Shubham Jain, Alberto Mannari, Hoang Tran, Yulong Li, Eri Ogawa, Kazuaki Ishizaki, Hiroshi Inoue, Marcel Schaal, Mauricio J. Serrano, Jungwook Choi, Xiao Sun, Naigang Wang, Chia-Yu Chen, Allison Allain, James Bonanno, Nianzheng Cao, Robert Casatuta, Matthew Cohen, Bruce M. Fleischer, Michael Guillorn, Howard Haynie, Jinwook Jung, Mingu Kang, Kyu-Hyoun Kim, Siyu Koswatta, Sae Kyu Lee, Martin Lutz, Silvia M. Mueller, Jinwook Oh, Ashish Ranjan, Zhibin Ren, Scot Rider, Kerstin Schelm, Michael Scheuermann, Joel Silberman, Jie Yang, Vidhi Zalani, Xin Zhang, Ching Zhou, Matthew M. Ziegler, Vinay Shah, Moriyoshi Ohara, Pong-Fei Lu, Brian W. Curran, Sunil Shukla, Leland Chang, Kailash Gopalakrishnan

Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

Online and Offline Machine Learning for Industrial Design Flow Tuning: (Invited - ICCAD Special Session Paper).

Matthew M. Ziegler, Jihye Kwon, Hung-Yi Liu, Luca P. Carloni

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

2020

Efficient AI System Design With Cross-Layer Approximate Computing.

Swagath Venkataramani, Xiao Sun, Naigang Wang, Chia-Yu Chen, Jungwook Choi, Mingu Kang, Ankur Agarwal, Jinwook Oh, Shubham Jain, Tina Babinsky, Nianzheng Cao, Thomas W. Fox, Bruce M. Fleischer, George Gristede, Michael Guillorn, Howard Haynie, Hiroshi Inoue, Kazuaki Ishizaki, Michael J. Klaiber, Shih-Hsien Lo, Gary W. Maier, Silvia M. Mueller, Michael Scheuermann, Eri Ogawa, Marcel Schaal, Mauricio J. Serrano, Joel Silberman, Christos Vezyrtzis, Wei Wang, Fanchieh Yee, Jintao Zhang, Matthew M. Ziegler, Ching Zhou, Moriyoshi Ohara, Pong-Fei Lu, Brian W. Curran, Sunil Shukla, Vijayalakshmi Srinivasan, Leland Chang, Kailash Gopalakrishnan

Proc. IEEE, 2020

A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference.

Jinwook Oh, Sae Kyu Lee, Mingu Kang, Matthew M. Ziegler, Joel Silberman, Ankur Agrawal, Swagath Venkataramani, Bruce M. Fleischer, Michael Guillorn, Jungwook Choi, Wei Wang, Silvia M. Mueller, Shimon Ben-Yehuda, James Bonanno, Nianzheng Cao, Robert Casatuta, Chia-Yu Chen, Matt Cohen, Ophir Erez, Thomas W. Fox, George Gristede, Howard Haynie, Vicktoria Ivanov, Siyu Koswatta, Shih-Hsien Lo, Martin Lutz, Gary W. Maier, Alex Mesh, Yevgeny Nustov, Scot Rider, Marcel Schaal, Michael Scheuermann, Xiao Sun, Naigang Wang, Fanchieh Yee, Ching Zhou, Vinay Shah, Brian W. Curran, Vijayalakshmi Srinivasan, Pong-Fei Lu, Sunil Shukla, Kailash Gopalakrishnan, Leland Chang

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

2019

Research From the IEEE IBM AI Compute and Emerging Technology Symposia.

Matthew M. Ziegler, Krishnan Kailas, Xin Zhang, Rajiv V. Joshi

IEEE J. Emerg. Sel. Topics Circuits Syst., 2019

Conference Report from the 2019 International Symposium on Low Power Electronics and Design (ISLPED).

Andreas Burg, Matthew M. Ziegler, Saibal Mukhopdhyay

IEEE Des. Test, 2019

Low Power Design From Moore to AI for nm Era : Invited Paper.

Rajiv V. Joshi, Matthew M. Ziegler

Proceedings of the 26th International Conference on Mixed Design of Integrated Circuits and Systems, 2019

Resilient Low Voltage Accelerators for High Energy Efficiency.

Nandhini Chandramoorthy, Karthik Swaminathan, Martin Cochet, Arun Paidimarri, Schuyler Eldridge, Rajiv V. Joshi, Matthew M. Ziegler, Alper Buyuktosunoglu, Pradip Bose

Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

A Learning-Based Recommender System for Autotuning Design Flows of Industrial High-Performance Processors.

Jihye Kwon, Matthew M. Ziegler, Luca P. Carloni

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference.

Bruce M. Fleischer, Sunil Shukla, Matthew M. Ziegler, Joel Silberman, Jinwook Oh, Vijayalakshmi Srinivasan, Jungwook Choi, Silvia M. Mueller, Ankur Agrawal, Tina Babinsky, Nianzheng Cao, Chia-Yu Chen, Pierce Chuang, Thomas W. Fox, George Gristede, Michael Guillorn, Howard Haynie, Michael J. Klaiber, Dongsoo Lee, Shih-Hsien Lo, Gary W. Maier, Michael Scheuermann, Swagath Venkataramani, Christos Vezyrtzis, Naigang Wang, Fanchieh Yee, Ching Zhou, Pong-Fei Lu, Brian W. Curran, Leland Chang, Kailash Gopalakrishnan

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

Across the Stack Opportunities for Deep Learning Acceleration.

Vijayalakshmi Srinivasan, Bruce M. Fleischer, Sunil Shukla, Matthew M. Ziegler, Joel Silberman, Jinwook Oh, Jungwook Choi, Silvia M. Mueller, Ankur Agrawal, Tina Babinsky, Nianzheng Cao, Chia-Yu Chen, Pierce Chuang, Thomas W. Fox, George Gristede, Michael Guillorn, Howard Haynie, Michael J. Klaiber, Dongsoo Lee, Shih-Hsien Lo, Gary W. Maier, Michael Scheuermann, Swagath Venkataramani, Christos Vezyrtzis, Naigang Wang, Fanchieh Yee, Ching Zhou, Pong-Fei Lu, Brian W. Curran, Leland Chang, Kailash Gopalakrishnan

Proceedings of the International Symposium on Low Power Electronics and Design, 2018

Cascaded and resonant SRAM supply boosting for ultra-low voltage cognitive IoT applications.

Rajiv V. Joshi, Matthew M. Ziegler, Karthik Swaminathan, Nandhini Chandramoorthy

Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2017

A Low Voltage SRAM Using Resonant Supply Boosting.

Rajiv V. Joshi, Matthew M. Ziegler, Holger Wetter

IEEE J. Solid State Circuits, 2017

Machine learning techniques for taming the complexity of modern hardware design.

Matthew M. Ziegler, Ramon Bertran Monfort, Alper Buyuktosunoglu, Pradip Bose

IBM J. Res. Dev., 2017

Very Low Voltage (VLV) Design.

Ramon Bertran, Pradip Bose, David M. Brooks, Jeff Burns, Alper Buyuktosunoglu, Nandhini Chandramoorthy, Eric Cheng, Martin Cochet, Schuyler Eldridge, Daniel Friedman, Hans M. Jacobson, Rajiv V. Joshi, Subhasish Mitra, Robert K. Montoye, Arun Paidimarri, Pritish Parida, Kevin Skadron, Mircea Stan, Karthik Swaminathan, Augusto Vega, Swagath Venkataramani, Christos Vezyrtzis, Gu-Yeon Wei, John-David Wellman, Matthew M. Ziegler

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Programmable supply boosting techniques for near threshold and wide operating voltage SRAM.

Rajiv V. Joshi, Matthew M. Ziegler

Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016

Early Scenario Pruning for Efficient Design Space Exploration in Physical Synthesis.

Mohd Anwar, Sourav Saha, Matthew M. Ziegler, Lakshmi N. Reddy

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Scalable Auto-Tuning of Synthesis Parameters for Optimizing High-Performance Processors.

Matthew M. Ziegler, Hung-Yi Liu, Luca P. Carloni

Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

A Scalable Black-Box Optimization System for Auto-Tuning VLSI Synthesis Programs.

Matthew M. Ziegler, Hung-Yi Liu, George Gristede, Bruce Owens, Ricardo Nigaglioni, Luca P. Carloni

Proceedings of the 1st International Workshop on RESource Awareness and Application Auto-tuning in Adaptive and heterogeNeous compuTing co-located with 19th International Conference on Design, 2016

A synthesis-parameter tuning system for autonomous design-space exploration.

Matthew M. Ziegler, Hung-Yi Liu, George Gristede, Bruce Owens, Ricardo Nigaglioni, Luca P. Carloni

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015

Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction.

Rajiv V. Joshi, Keunwoo Kim, Rouwaida Kanj, Ajay N. Bhoj, Matthew M. Ziegler, Phil Oldiges, Pranita Kerber, Robert Wong, Terence Hook, Sudesh Saroop, Carl Radens, Chun-Chen Yeh

IEEE Trans. Very Large Scale Integr. Syst., 2015

IBM POWER8 circuit design and energy optimization.

Victor V. Zyuban, Joshua Friedrich, Daniel M. Dreps, Jürgen Pille, Donald W. Plass, Phillip J. Restle, Zeynep Toprak Deniz, Matthew M. Ziegler, Sam G. Chu, Md. Saiful Islam, James D. Warnock, Bob Philhower, Rahul M. Rao, Gregory S. Still, David Shan, Eric Fluhr, Jose Paredes, Dieter F. Wendel, Christopher J. Gonzalez, D. Hogenmiller, Ruchir Puri, Scott A. Taylor, Stephen D. Posluszny

IBM J. Res. Dev., 2015

IBM z13 circuit design and methodology.

James D. Warnock, Christopher J. Berry, Michael H. Wood, Leon J. Sigal, Yun-Chan Myung, Guenter Mayer, Mark D. Mayo, Y. Chan, Frank Malgioglio, Gerald Strevig, Charudhattan Nagarajan, Sean M. Carey, Gerard Salem, Friedrich Schroeder, Howard H. Smith, Di Phan, Ricardo Nigaglioni, Thomas Strach, Matthew M. Ziegler, Niels Fricke, K. Lind, José Neves, Sridhar H. Rangarajan, J. P. Surprise, John Isakson, John Badar, Doug Malone, Donald W. Plass, A. Aipperspach, Dieter F. Wendel, Robert M. Averill III, Ruchir Puri

IBM J. Res. Dev., 2015

14nm FinFET based supply voltage boosting techniques for extreme low Vmin operation.

Rajiv V. Joshi, Matthew M. Ziegler, Holger Wetter, C. Wandel, Herschel A. Ainspan

Proceedings of the Symposium on VLSI Circuits, 2015

4.1 22nm Next-generation IBM System z microprocessor.

James D. Warnock, Brian W. Curran, John Badar, Gregory Fredeman, Donald W. Plass, Yuen H. Chan, Sean M. Carey, Gerard Salem, Friedrich Schroeder, Frank Malgioglio, Guenter Mayer, Christopher J. Berry, Michael H. Wood, Yiu-Hing Chan, Mark D. Mayo, John Isakson, Charudhattan Nagarajan, Tobias Werner, Leon J. Sigal, Ricardo Nigaglioni, Mark Cichanowski, Jeffrey A. Zitz, Matthew M. Ziegler, Tim Bronson, Gerald Strevig, Daniel Dreps, Ruchir Puri, Douglas Malone, Dieter F. Wendel, Pak-kin Mak, Michael A. Blake

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014

5.1 POWER8^TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth.

Eric J. Fluhr, Joshua Friedrich, Daniel M. Dreps, Victor V. Zyuban, Gregory S. Still, Christopher J. Gonzalez, Allen Hall, David Hogenmiller, Frank Malgioglio, Ryan Nett, Jose Paredes, Juergen Pille, Donald W. Plass, Ruchir Puri, Phillip J. Restle, David Shan, Kevin Stawiasz, Zeynep Toprak Deniz, Dieter F. Wendel, Matthew M. Ziegler

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Bridging high performance and low power in processor design.

Ruchir Puri, Mihir R. Choudhury, Haifeng Qian, Matthew M. Ziegler

Proceedings of the International Symposium on Low Power Electronics and Design, 2014

The POWER8^TM processor: Designed for big data, analytics, and cloud environments.

Joshua Friedrich, Hung Q. Le, William J. Starke, Jeff Stuecheli, Balaram Sinharoy, Eric J. Fluhr, Daniel M. Dreps, Victor V. Zyuban, Gregory S. Still, Christopher J. Gonzalez, David Hogenmiller, Frank Malgioglio, Ryan Nett, Ruchir Puri, Phillip J. Restle, David Shan, Zeynep Toprak Deniz, Dieter F. Wendel, Matthew M. Ziegler, Dave W. Victor

Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

POWER8 design methodology innovations for improving productivity and reducing power.

Matthew M. Ziegler, Ruchir Puri, Bob Philhower, Robert L. Franch, Wing K. Luk, Jens Leenstra, Peter Verwegen, Niels Fricke, George Gristede, Eric Fluhr, Victor V. Zyuban

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013

Network flow based datapath bit slicing.

Hua Xiang, Minsik Cho, Haoxing Ren, Matthew M. Ziegler, Ruchir Puri

Proceedings of the International Symposium on Physical Design, 2013

Power reduction by aggressive synthesis design space exploration.

Matthew M. Ziegler, George Gristede, Victor V. Zyuban

Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

LatchPlanner: latch placement algorithm for datapath-oriented high-performance VLSI designs.

Minsik Cho, Hua Xiang, Haoxing Ren, Matthew M. Ziegler, Ruchir Puri

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

2009

A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR).

Milena Vratonjic, Matthew M. Ziegler, George Gristede, Victor V. Zyuban, Thomas Mitchell, Ee Cho, Chandu Visweswariah, Vojin G. Oklobdzija

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

The opportunity cost of low power design: a case study in circuit tuning.

Matthew M. Ziegler, Victor V. Zyuban, George Gristede, Milena Vratonjic, Joshua Friedrich

Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

2008

A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing.

Azeez J. Bhavnagarwala, Stephen Kosonocky, Carl Radens, Yuen H. Chan, Kevin Stawiasz, Uma Srinivasan, Steven P. Kowalczyk, Matthew M. Ziegler

IEEE J. Solid State Circuits, 2008

2007

Multi-Dimensional Circuit and Micro-Architecture Level Optimization.

Zhenyu Qi, Matthew M. Ziegler, Stephen V. Kosonocky, Jan M. Rabaey, Mircea R. Stan

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Structured and tuned array generation (STAG) for high-performance random logic.

Matthew M. Ziegler, Gary S. Ditlow, Stephen V. Kosonocky, Zhenyu Qi, Mircea R. Stan

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

2006

Hybrid CMOS/Molecular Electronic Circuits.

Mircea R. Stan, Garrett S. Rose, Matthew M. Ziegler

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

2004

Large-signal two-terminal device model for nanoelectronic circuit analysis.

Garrett S. Rose, Matthew M. Ziegler, Mircea R. Stan

IEEE Trans. Very Large Scale Integr. Syst., 2004

A Unified Design Space for Regular Parallel Prefix Adders.

Matthew M. Ziegler, Mircea R. Stan

Proceedings of the 2004 Design, 2004

2003

Molecular electronics: from devices and interconnect to circuits and architecture.

Mircea R. Stan, Paul D. Franzon, Seth Copen Goldstein, John C. Lach, Matthew M. Ziegler

Proc. IEEE, 2003

The CMOS/nano interface from a circuits perspective.

Matthew M. Ziegler, Mircea R. Stan

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002

A Case for CMOS/nano co-design.

Matthew M. Ziegler, Mircea R. Stan

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

2001

Optimal logarithmic adder structures with a fanout of two for minimizing the area-delay product.

Matthew M. Ziegler, Mircea Stan

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001