Matthew J. Thazhuthaveetil

According to our database, Matthew J. Thazhuthaveetil authored at least 29 papers between 1986 and 2024.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2024

Tile Size and Loop Order Selection using Machine Learning for Multi-/Many-Core Architectures.

Shilpa Babalad, Shirish K. Shevade, Matthew Jacob Thazhuthaveetil, R. Govindarajan

Proceedings of the 38th ACM International Conference on Supercomputing, 2024

2014

Preemptive thread block scheduling with online structural runtime prediction for concurrent GPGPU kernels.

Sreepathi Pai, R. Govindarajan, Matthew J. Thazhuthaveetil

Proceedings of the International Conference on Parallel Architectures and Compilation, 2014

2013

Improving GPGPU concurrency with elastic kernels.

Sreepathi Pai, Matthew J. Thazhuthaveetil, R. Govindarajan

Proceedings of the Architectural Support for Programming Languages and Operating Systems, 2013

2012

CUDA-For-Clusters: A System for Efficient Execution of CUDA Kernels on Multi-core Clusters.

Raghu Prabhakar, R. Govindarajan, Matthew J. Thazhuthaveetil

Proceedings of the Euro-Par 2012 Parallel Processing - 18th International Conference, 2012

Fast and efficient automatic memory management for GPUs using compiler-assisted runtime coherence scheme.

Sreepathi Pai, R. Govindarajan, Matthew J. Thazhuthaveetil

Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2009

Synergistic execution of stream programs on multicores with accelerators.

Abhishek Udupa, R. Govindarajan, Matthew J. Thazhuthaveetil

Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, 2009

Software Pipelined Execution of Stream Programs on GPUs.

Abhishek Udupa, R. Govindarajan, Matthew J. Thazhuthaveetil

Proceedings of the CGO 2009, 2009

2008

Impact of message compression on the scalability of an atmospheric modeling application on clusters.

V. Santhosh Kumar, Ravi S. Nanjundiah, Matthew J. Thazhuthaveetil, R. Govindarajan

Parallel Comput., 2008

2007

Microarchitecture Sensitive Empirical Models for Compiler Optimizations.

Kapil Vaswani, Matthew J. Thazhuthaveetil, Y. N. Srikant, P. J. Joseph

Proceedings of the Fifth International Symposium on Code Generation and Optimization (CGO 2007), 2007

2006

A Predictive Performance Model for Superscalar Processors.

P. J. Joseph, Kapil Vaswani, Matthew J. Thazhuthaveetil

Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006

Exploiting programmable network interfaces for parallel query execution in workstation clusters.

V. Santhosh Kumar, Matthew J. Thazhuthaveetil, R. Govindarajan

Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Construction and use of linear regression models for processor performance analysis.

P. J. Joseph, Kapil Vaswani, Matthew J. Thazhuthaveetil

Proceedings of the 12th International Symposium on High-Performance Computer Architecture, 2006

2005

Offloading Bloom Filter Operations to Network Processor for Parallel Query Processing in Cluster of Workstations.

V. Santhosh Kumar, Matthew J. Thazhuthaveetil, R. Govindarajan

Proceedings of the High Performance Computing, 2005

A Programmable Hardware Path Profiler.

Kapil Vaswani, Matthew J. Thazhuthaveetil, Y. N. Srikant

Proceedings of the 3nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2005), 2005

2001

TWLinuX : Operating System Support for Optimistic Parallel Discrete Event Simulation.

Subramania Sharma, Matthew Thazhuthaveetil

Proceedings of the High Performance Computing - HiPC 2001, 8th International Conference, 2001

1995

Cache Coherence in Multiprocessors: A Survey.

Mazin S. Yousif, Matthew Thazhuthaveetil, Chita R. Das

Adv. Comput., 1995

1994

A Cache coherence protocol for MIN-based multiprocessors.

Mazin S. Yousif, Chita R. Das, Matthew J. Thazhuthaveetil

J. Supercomput., 1994

Design of an MS-DOS PC program profiler.

K. V. Subramaniam, Matthew J. Thazhuthaveetil

Microprocess. Microsystems, 1994

1993

A Cache Coherence Protocol for MIN-Based Multprocessors With Limited Inclusion.

Mazin S. Yousif, Chita R. Das, Matthew Thazhuthaveetil

Proceedings of the 1993 International Conference on Parallel Processing, 1993

1991

Parallel hough transform algorithm performance.

Matthew J. Thazhuthaveetil, Anish V. Shah

Image Vis. Comput., 1991

Effect of Hot Spots on Multiprocessor Systems Using Circuit Switched Interconnection Networks.

Lizyamma Kurian, Matthew Thazhuthaveetil

Proceedings of the International Conference on Parallel Processing, 1991

A Cache-Based Checkpointing Scheme for MIN-Based Multiprocessors.

Mazin S. Algudady, Chita R. Das, Matthew Thazhuthaveetil

Proceedings of the International Conference on Parallel Processing, 1991

1990

Application-dependent simulation of microprocessor-based multiprocessors.

Jeffrey T. Kreulen, Matthew J. Thazhuthaveetil

Microprocess. Microsystems, 1990

Dependability Modeling for Multiprocessors.

Chita R. Das, Jeffrey T. Kreulen, Matthew Thazhuthaveetil, Laxmi N. Bhuyan

Computer, 1990

A write update cache coherence protocol for MIN-based multiprocessors with accessibility-based split caches.

Mazin S. Algudady, Chita R. Das, Matthew Thazhuthaveetil

Proceedings of the Proceedings Supercomputing '90, New York, NY, USA, November 12-16, 1990, 1990

Hotspot Contention in Non-Blocking Multistage Interconnection Networks.

Robert L. Lesher, Matthew Thazhuthaveetil

Proceedings of the 1990 International Conference on Parallel Processing, 1990

1987

On the Structural Locality of Reference in LISP List Access Streams.

Matthew Thazhuthaveetil, Andrew R. Pleszkun

Inf. Process. Lett., 1987

The Architecture of Lisp Machines.

Andrew R. Pleszkun, Matthew Thazhuthaveetil

Computer, 1987

1986

An Architecture for Efficient Lisp List Access.

Andrew R. Pleszkun, Matthew Thazhuthaveetil

Proceedings of the 13th Annual Symposium on Computer Architecture, Tokyo, Japan, June 1986, 1986