Matthew I. Frank

Affiliations:
  • University of Illinois at Urbana-Champaign, Urbana, IL, USA
  • Massachusetts Institute of Technology, Cambridge, MA, USA (former)


According to our database1, Matthew I. Frank authored at least 26 papers between 1993 and 2011.

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Bibliography

2011
Demand-driven software race detection using hardware performance counters.
Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

2010
A Task-Centric Memory Model for Scalable Accelerator Architectures.
IEEE Micro, 2010

2009

Rigel: an architecture and scalable programming interface for a 1000-core accelerator.
Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

SPARTAN: A software tool for Parallelization Bottleneck Analysis.
Proceedings of the 2009 ICSE Workshop on Multicore Software Engineering, 2009

Emµcode: Masking hard faults in complex functional units.
Proceedings of the 2009 IEEE/IFIP International Conference on Dependable Systems and Networks, 2009

2008
Fetch-Criticality Reduction through Control Independence.
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008

Branch-mispredict level parallelism (BLP) for control independence.
Proceedings of the 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 2008

PaCo: Probability-based path confidence prediction.
Proceedings of the 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 2008

2007
Automatic Discovery of Coarse-Grained Parallelism in Media Applications.
Trans. High Perform. Embed. Archit. Compil., 2007

Exploiting Postdominance for Speculative Parallelization.
Proceedings of the 13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 2007

Implicitly Parallel Programming Models for Thousand-Core Microprocessors.
Proceedings of the 44th Design Automation Conference, 2007

2005
Address-Indexed Memory Disambiguation and Store-to-Load Forwarding.
Proceedings of the 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-38 2005), 2005

2004
Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams.
Proceedings of the 31st International Symposium on Computer Architecture (ISCA 2004), 2004

2003
SUDS: automatic parallelization for raw processors.
PhD thesis, 2003

2002
The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs.
IEEE Micro, 2002

2001
LoGPC: Modeling Network Contention in Message-Passing Programs.
IEEE Trans. Parallel Distributed Syst., 2001

2000
FlexCache: A Framework for Flexible Compiler Generated Data Caching.
Proceedings of the Intelligent Memory Systems, Second International Workshop, 2000

1999
Parallelizing Applications into Silicon.
Proceedings of the 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 1999

1998
Exploiting Two-Case Delivery for Fast Protected Messaging.
Proceedings of the Fourth International Symposium on High-Performance Computer Architecture, Las Vegas, Nevada, USA, January 31, 1998

Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine.
Proceedings of the ASPLOS-VIII Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems, 1998

1997
Baring It All to Software: Raw Machines.
Computer, 1997

LoPC: Modeling Contention in Parallel Algorithms.
Proceedings of the Sixth ACM SIGPLAN Symposium on Principles & Practice of Parallel Programming (PPOPP), 1997

Implications of I/O for Gang Scheduled Workloads.
Proceedings of the Job Scheduling Strategies for Parallel Processing, 1997

The RAW benchmark suite: computation structures for general purpose computing.
Proceedings of the 5th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '97), 1997

1993
A Hybrid Shared Memory/Message Passing Parallel Machine.
Proceedings of the 1993 International Conference on Parallel Processing, 1993


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