Matthew Baecher

According to our database, Matthew Baecher authored at least 2 papers between 2014 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2024

A 1.1pJ/b/Lane, 1.8Tb/s Chiplet Over XSR-MCM Channels Using 113Gb/s PAM-4 Transceiver with Signal Equalization and Envelope Adaptation Using TX-FFE in 5nm CMOS.

Gautam R. Gangasani, A. Mostafa, A. Singh, Daniel W. Storaska, D. Prabakaran, K. Mohammad, Matthew Baecher, M. Shannon, Michael Sorna, Michael Wielgos, P. Jenkins, P. B. Ramakrishna, U. K. Shukla

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2014

A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology.

Gautam R. Gangasani, Chun-Ming Hsu, John F. Bulzacchelli, Troy J. Beukema, William R. Kelly, Hui H. Xu, David Freitas, Andrea Prati, Daniele Gardellini, Robert Reutemann, Giovanni Cervelli, Juergen Hertle, Matthew Baecher, Jon Garlett, Pier Andrea Francese, John F. Ewen, David Hanson, Daniel W. Storaska, Mounir Meghelli

IEEE J. Solid State Circuits, 2014