Matteo Repossi
Orcid: 0000-0002-3404-5085
According to our database1,
Matteo Repossi
authored at least 20 papers
between 2007 and 2022.
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Collaborative distances:
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Bibliography
2022
Analog Front End of 50-Gb/s SiGe BiCMOS Opto-Electrical Receiver in 3-D-Integrated Silicon Photonics Technology.
IEEE J. Solid State Circuits, 2022
2020
12.2 A 4-Channel 200Gb/s PAM-4 BiCMOS Transceiver with Silicon Photonics Front-Ends for Gigabit Ethernet Applications.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
A 26-Gb/s 3-D-Integrated Silicon Photonic Receiver in BiCMOS-55 nm and PIC25G With - 15.2-dBm OMA Sensitivity.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
2016
Insights Into Silicon Photonics Mach-Zehnder-Based Optical Transmitter Architectures.
IEEE J. Solid State Circuits, 2016
23.4 A 56Gb/s 300mW silicon-photonics transmitter in 3D-integrated PIC25G and 55nm BiCMOS technologies.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
A 25Gb/s 3D-integrated silicon photonics receiver in 65nm CMOS and PIC25G for 100GbE optical links.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
22.9 A 1310nm 3D-integrated silicon photonics Mach-Zehnder-based transmitter with 275mW multistage CMOS driver achieving 6dB extinction ratio at 25Gb/s.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2014
IEEE J. Solid State Circuits, 2014
A 3D-integrated 25Gbps silicon photonics receiver in PIC25G and 65nm CMOS technologies.
Proceedings of the ESSCIRC 2014, 2014
2012
Proceedings of the 38th European Solid-State Circuit conference, 2012
2011
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
IEEE J. Solid State Circuits, 2011
2010
A wideband mm-Wave CMOS receiver for Gb/s communications employing interstage coupled resonators.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2009
Design of Low-Loss Transmission Lines in Scaled CMOS by Accurate Electromagnetic Simulations.
IEEE J. Solid State Circuits, 2009
A Multi-Standard 1.5 to 10 Gb/s Latch-Based 3-Tap DFE Receiver With a SSC Tolerant CDR for Serial Backplane Communication.
IEEE J. Solid State Circuits, 2009
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
2008
A 24GHz Sub-Harmonic Receiver Front-End with Integrated Multi-Phase LO Generation in 65nm CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007