Matteo Pisati

According to our database, Matteo Pisati authored at least 5 papers between 2005 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2020

A 243-mW 1.25-56-Gb/s Continuous Range PAM-4 42.5-dB IL ADC/DAC-Based Transceiver in 7-nm FinFET.

Matteo Pisati, Alberto Minuti, Giacomino Bollati, Fabio Giunco, Roberto G. Massolini, Giovanni Cesura, Fernando De Bernardinis, Paolo Pascale, Claudio Nani, Nicola Ghittori, Enrico Pozzati, Marco Sosio, Marco Garampazzi, Antonio Milani

IEEE J. Solid State Circuits, 2020

2019

A Sub-250mW 1-to-56Gb/s Continuous-Range PAM-4 42.5dB IL ADC/DAC-Based Transceiver in 7nm FinFET.

Matteo Pisati, Fernando De Bernardinis, Paolo Pascale, Claudio Nani, Marco Sosio, Enrico Pozzati, Nicola Ghittori, Federico Magni, Marco Garampazzi, Giacomino Bollati, Antonio Milani, Alberto Minuti, Fabio Giunco, Paola Uggetti, Ivan Fabiano, Nicola Codega, Alessandro Bosi, Nicola Carta, Demetrio Pellicone, Giorgio Spelgatti, Massimo Cutrupi, Andrea Rossini, Roberto G. Massolini, Giovanni Cesura, Ivan Bietti

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2009

A Multi-Standard 1.5 to 10 Gb/s Latch-Based 3-Tap DFE Receiver With a SSC Tolerant CDR for Serial Backplane Communication.

Massimo Pozzoni, Simone Erba, Paolo Viola, Matteo Pisati, Emanuele Depaoli, Davide Sanzogni, Riccardo Brama, Daniele Baldi, Matteo Repossi, Francesco Svelto

IEEE J. Solid State Circuits, 2009

2008

A 10Gb/s receiver with linear backplane equalization and mixer-based self-aligned CDR.

Simone Erba, Massimo Pozzoni, Matteo Pisati, Riccardo Brama, Davide Sanzogni, Emanuele Depaoli, Paolo Viola, Francesco Svelto

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2005

Circuits for high speed serial communications.

Matteo Pisati

PhD thesis, 2005