Matt Grange

According to our database, Matt Grange authored at least 10 papers between 2009 and 2015.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2015

Zero-load predictive model for performance analysis in deflection routing NoCs.

Awet Yemane Weldezion, Matt Grange, Axel Jantsch, Hannu Tenhunen, Dinesh Pamunuwa

Microprocess. Microsystems, 2015

2013

A scalable multi-dimensional NoC simulation model for diverse spatio-temporal traffic patterns.

Awet Yemane Weldezion, Matt Grange, Dinesh Pamunuwa, Axel Jantsch, Hannu Tenhunen

Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2011

The Promises and Limitations of 3-D Integration.

Axel Jantsch, Matthew Grange, Dinesh Pamunuwa

Proceedings of the 3D Integration for NoC-based SoC Architectures, 2011

3-D integration and the limits of silicon computation.

Dinesh Pamunuwa, Matthew Grange, Roshan Weerasekera, Axel Jantsch

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Optimal network architectures for minimizing average distance in k-ary n-dimensional mesh networks.

Matt Grange, Roshan Weerasekera, Dinesh Pamunuwa, Axel Jantsch, Awet Yemane Weldezion

Proceedings of the NOCS 2011, 2011

Modeling the computational efficiency of 2-D and 3-D silicon processors for early-chip planning.

Matthew Grange, Axel Jantsch, Roshan Weerasekera, Dinesh Pamunuwa

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2010

On signalling over Through-Silicon Via (TSV) interconnects in 3-D Integrated Circuits.

Roshan Weerasekera, Matt Grange, Dinesh Pamunuwa, Hannu Tenhunen

Proceedings of the Design, Automation and Test in Europe, 2010

2009

Scalability of network-on-chip communication architecture for 3-D meshes.

Awet Yemane Weldezion, Matt Grange, Dinesh Pamunuwa, Zhonghai Lu, Axel Jantsch, Roshan Weerasekera, Hannu Tenhunen

Proceedings of the Third International Symposium on Networks-on-Chips, 2009

Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits.

Roshan Weerasekera, Matt Grange, Dinesh Pamunuwa, Hannu Tenhunen, Li-Rong Zheng

Proceedings of the IEEE International Conference on 3D System Integration, 2009

Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh.

Matt Grange, Awet Yemane Weldezion, Dinesh Pamunuwa, Roshan Weerasekera, Zhonghai Lu, Axel Jantsch, Dave Shippen

Proceedings of the IEEE International Conference on 3D System Integration, 2009