Mats Torkelson

According to our database, Mats Torkelson authored at least 16 papers between 1993 and 2000.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2000

A low logic depth complex multiplier using distributed arithmetic.

Anders Berkeman, Viktor Öwall, Mats Torkelson

IEEE J. Solid State Circuits, 2000

A digitally controlled low-power clock multiplier for globally asynchronous locally synchronous designs.

Thomas Olsson, Peter Nilsson, Thomas Meincke, Ahmad Hemami, Mats Torkelson

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999

A Custom Image Convolution DSP with a Sustained Calculation Capacity of >1 GMAC/s and Low I/O Bandwidth.

Viktor Öwall, Mats Torkelson, Peter Egelberg

J. VLSI Signal Process., 1999

An Orthogonal Time-Frequency Extraction Approach to 2D Systolic Architecture for 1D DFT Computation.

Shousheng He, Mats Torkelson

J. VLSI Signal Process., 1999

1998

A complex multiplier with low logic depth.

Anders Berkeman, Viktor Öwall, Mats Torkelson

Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

Design and implementation of a 1024-point pipeline FFT processor.

Shousheng He, Mats Torkelson

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998

1997

A custom digital intermediate frequency filter for the American mobile telephone system.

Peter Nilsson, Mats Torkelson

IEEE J. Solid State Circuits, 1997

1996

Computing partial DFT for comb spectrum evaluation.

Shousheng He, Mats Torkelson

IEEE Signal Process. Lett., 1996

A monolithic digital clock-generator for on-chip clocking of custom DSP's.

Peter Nilsson, Mats Torkelson

IEEE J. Solid State Circuits, 1996

A New Approach to Pipeline FFT Processor.

Shousheng He, Mats Torkelson

Proceedings of IPPS '96, 1996

Design of a fast and area efficient filter.

Pontus Åström, Peter Nilsson, Mats Torkelson

Proceedings of the 8th European Signal Processing Conference, 1996

1995

VLSI computation of the partial DFT for (de)modulation in multi-channel OFDM system.

Shousheng He, Mats Torkelson

Proceedings of the 6th IEEE International Symposium on Personal, 1995

A Pipelined Bit-Serial Complex Multiplier Using Distributed Arithmetic.

Shousheng He, Mats Torkelson

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994

A systolic array implementation of common factor algorithm to compute DFT.

Shousheng He, Mats Torkelson

Proceedings of the International Symposium on Parallel Architectures, 1994

A Bit-Serial CMOS Digital IF-Filter for Mobile Radio Using an On-Chip Clock.

Peter Nilsson, Mats Torkelson, Kent Palmkvist, Mark Vesterbacka, Lars Wanhammar

Proceedings of the Mobile Communications: Advanced Systems and Components, 1994

1993

A GSM speech coder implemented on a customized processor architecture.

Viktor Öwall, Pietro Andreani, L. Brange, Peter Nilsson, A. Wass, Mats Torkelson

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993