Mats Brorsson
Orcid: 0000-0002-9637-2065
According to our database1,
Mats Brorsson
authored at least 66 papers
between 1991 and 2024.
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Bibliography
2024
ACM Trans. Archit. Code Optim., June, 2024
CoRR, 2024
2023
CoRR, 2023
Performance Analysis and Benchmarking of a Temperature Downscaling Deep Learning Model.
Proceedings of the 31st Euromicro International Conference on Parallel, 2023
Proceedings of the IEEE International Conference on Cloud Engineering, 2023
DIPPM: A Deep Learning Inference Performance Predictive Model Using Graph Neural Networks.
Proceedings of the Euro-Par 2023: Parallel Processing - 29th International Conference on Parallel and Distributed Computing, Limassol, Cyprus, August 28, 2023
2022
Auto-clustering of Financial Reports Based on Formatting Style and Author's Fingerprint.
Proceedings of the Machine Learning and Principles and Practice of Knowledge Discovery in Databases, 2022
Proceedings of the 42nd IEEE International Conference on Distributed Computing Systems, 2022
2021
An ASIC Implementation and Evaluation of a Profiled Low-Energy Instruction Set Architecture Extension.
CoRR, 2021
2020
Proceedings of the 28th Euromicro International Conference on Parallel, 2020
2019
J. Circuits Syst. Comput., 2019
Infer Your Enemies and Know Yourself, Learning in Real-Time Bidding with Partially Observable Opponents.
CoRR, 2019
Proceedings of the 2019 International Conference on Data Mining Workshops, 2019
Proceedings of the 27th European Symposium on Artificial Neural Networks, 2019
2018
Computing, 2018
2017
Proceedings of the International Symposium on Memory Systems, 2017
Proceedings of the Advanced Data Mining and Applications - 13th International Conference, 2017
2016
Architectural Impact on Performance of In-memory Data Analytics: Apache Spark Case Study.
CoRR, 2016
Concurr. Comput. Pract. Exp., 2016
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016
Proceedings of the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2016
Micro-Architectural Characterization of Apache Spark on Batch and Stream Processing Workloads.
Proceedings of the 2016 IEEE International Conferences on Big Data and Cloud Computing (BDCloud), 2016
Proceedings of the 3rd IEEE/ACM International Conference on Big Data Computing, 2016
Proceedings of the 3rd IEEE/ACM International Conference on Big Data Computing, 2016
2015
Locality-Aware Task Scheduling and Data Distribution for OpenMP Programs on NUMA Systems and Manycore Processors.
Sci. Program., 2015
A comparative performance study of common and popular task-centric programming frameworks.
Concurr. Comput. Pract. Exp., 2015
Proceedings of the 44th International Conference on Parallel Processing, 2015
Proceedings of the Big Data Benchmarks, Performance Optimization, and Emerging Hardware, 2015
Proceedings of the Fifth IEEE International Conference on Big Data and Cloud Computing, 2015
2014
TurboBŁYSK: Scheduling for Improved Data-Driven Task Performance with Fast Dependency Resolution.
Proceedings of the Using and Improving OpenMP for Devices, Tasks, and More, 2014
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014
2013
Proceedings of the OpenMP in the Era of Low Power Devices and Accelerators, 2013
2012
Proceedings of the OpenMP in a Heterogeneous World - 8th International Workshop on OpenMP, 2012
Proceedings of the Euro-Par 2012: Parallel Processing Workshops, 2012
Proceedings of the Euro-Par 2012: Parallel Processing Workshops, 2012
2011
Proceedings of the 2011 International Green Computing Conference and Workshops, 2011
2009
Two-Level Dictionary Code Compression: A New Scheme to Improve Instruction Code Density of Embedded Applications.
Proceedings of the CGO 2009, 2009
2008
SIGARCH Comput. Archit. News, 2008
Proceedings of the 13th Asia-Pacific Computer Systems Architecture Conference, 2008
Improving code density of embedded software using a 2-level dictionary code compression architecture.
Proceedings of the 13th Asia-Pacific Computer Systems Architecture Conference, 2008
2006
Proceedings of the 2006 International Conference on Compilers, 2006
2004
A Multiprogrammed Workload Model for Energy and Performance Estimation of Adaptive Chip-Multiprocessors.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004
Proceedings of the 2004 Design, 2004
2003
Clust. Comput., 2003
2002
MipsIt: a simulation and development environment using animation for computer architecture education.
Proceedings of the 2002 workshop on Computer architecture education, 2002
Memory Utilization in Software DSM for Embedded Systems.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2002
Proceedings of the High Performance Computing, 2002
Proceedings of the International Conference on Compilers, 2002
2000
Concurr. Pract. Exp., 2000
1999
J. Supercomput., 1999
Producer-Push - A Protocol Enhancement to Page-Based Software Distributed Shared Memory Systems.
Proceedings of the International Conference on Parallel Processing 1999, 1999
Programming Effort vs. Performance with a Hybrid Programming Model for Distributed Memory Parallel Architectures.
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999
1998
Visualization for Performance Tuning of DVSM System Applications on Networks of Workstations.
Proceedings of the Thirty-First Annual Hawaii International Conference on System Sciences, 1998
A Comparative Characterization of Communication Patterns in Applications Using MPI and Shared Memory on an IBM SP2.
Proceedings of the Network-Based Parallel Computing: Communication, 1998
1997
IBM Syst. J., 1997
1996
Parallel Comput., 1996
Proceedings of the MASCOTS '96, 1996
1995
SM-prof: A Tool to Visualise and Find Cache Coherence Performance Bottlenecks in Multiprocessor Programs.
Proceedings of the 1995 ACM SIGMETRICS joint international conference on Measurement and modeling of computer systems, 1995
1994
Modelling accesses to migratory and producer-consumer characterised data in a shared memory multiprocessor.
Proceedings of the Sixth IEEE Symposium on Parallel and Distributed Processing, 1994
1993
Proceedings of the 20th Annual International Symposium on Computer Architecture, 1993
The Cachemire Test Bench A Flexible And Effective Approach For Simulation Of Multiprocessors.
Proceedings of the Proceedings 26th Annual Simulation Symposium, ANSS 1993, 1993
1991
Proceedings of the Third IEEE Symposium on Parallel and Distributed Processing, 1991