Mathieu Gross

Orcid: 0000-0003-1468-6026

According to our database1, Mathieu Gross authored at least 10 papers between 2017 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
Remote Security Threats and Protection of Modern FPGA-SoC Architectures / Mathieu Etienne André Gross ; Gutachter: Georg Sigl, Walter Stechele ; Betreuer: Georg Sigl.
PhD thesis, 2023

CPU to FPGA Power Covert Channel in FPGA-SoCs.
IACR Cryptol. ePrint Arch., 2023

FPGANeedle: Precise Remote Fault Attacks from FPGA to CPU.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022
Enhancing the Security of FPGA-SoCs via the Usage of ARM TrustZone and a Hybrid-TPM.
ACM Trans. Reconfigurable Technol. Syst., 2022

Breaking TrustZone memory isolation and secure boot through malicious hardware on a modern FPGA-SoC.
J. Cryptogr. Eng., 2022

2021
Beyond Cache Attacks: Exploiting the Bus-based Communication Structure for Powerful On-Chip Microarchitectural Attacks.
ACM Trans. Embed. Comput. Syst., 2021

2019
Breaking TrustZone Memory Isolation through Malicious Hardware on a Modern FPGA-SoC.
Proceedings of the 3rd ACM Workshop on Attacks and Solutions in Hardware Security Workshop, 2019

2018
Where Technology Meets Security: Key Storage and Data Separation for System-on-Chips.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

2017
Towards trace-driven cache attacks on Systems-on-Chips - exploiting bus communication.
Proceedings of the 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2017

Exploiting Bus Communication to Improve Cache Attacks on Systems-on-Chips.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017


  Loading...