Mathias Soeken

According to our database, Mathias Soeken authored at least 181 papers between 2008 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2023

Using Azure Quantum Resource Estimator for Assessing Performance of Fault Tolerant Quantum Computation.

Wim van Dam, Mariia Mykhailova, Mathias Soeken

Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, 2023

2022

The multiplicative complexity of interval checking.

Thomas Häner, Mathias Soeken

IACR Cryptol. ePrint Arch., 2022

Advances in Quantum Computation and Quantum Technologies: A Design Automation Perspective.

Giovanni De Micheli, Jie-Hong R. Jiang, Robert Rand, Kaitlin N. Smith, Mathias Soeken

IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

Design and Automation for Quantum Computation and Quantum Technologies.

Jie-Hong R. Jiang, Giovanni De Micheli, Kaitlin N. Smith, Mathias Soeken

IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

Assessing requirements to scale to practical quantum advantage.

Michael E. Beverland, Prakash Murali, Matthias Troyer, Krysta M. Svore, Torsten Hoefler, Vadym Kliuchnikov, Guang Hao Low, Mathias Soeken, Aarthi Sundaram, Alexander Vaschillo

CoRR, 2022

Space-time optimized table lookup.

Thomas Häner, Vadym Kliuchnikov, Martin Roetteler, Mathias Soeken

CoRR, 2022

A Q# Implementation of a Quantum Lookup Table for Quantum Arithmetic Functions.

Rajiv Krishnakumar, Mathias Soeken, Martin Roetteler, William J. Zeng

CoRR, 2022

QParallel: Explicit Parallelism for Programming Quantum Computers.

Thomas Häner, Vadym Kliuchnikov, Martin Roetteler, Mathias Soeken, Alexander Vaschillo

CoRR, 2022

Automatic oracle generation in microsoft's quantum development kit using QIR and LLVM passes.

Mathias Soeken, Mariia Mykhailova

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

Three-Input Gates for Logic Synthesis.

Dewmini Sudara Marakkalage, Eleonora Testa, Heinz Riener, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Testing Quantum Programs using Q# and Microsoft Quantum Development Kit.

Mariia Mykhailova, Mathias Soeken

Proceedings of the Short Papers Proceedings of the 2nd International Workshop on Software Engineering & Technology (Q-SET 2021) co-located with IEEE International Conference on Quantum Computing and Engineering (IEEE Quantum Week 2021), 2021

A Resource Estimation and Verification Workflow in Q# Special session paper.

Mathias Soeken, Mariia Mykhailova, Vadym Kliuchnikov, Christopher E. Granade, Alexander Vaschillo

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

SAT-Based Exact Synthesis: Encodings, Topology Families, and Parallelism.

Winston Haaswijk, Mathias Soeken, Alan Mishchenko, Giovanni De Micheli

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Advanced Functional Decomposition Using Majority and Its Applications.

Zhufei Chu, Mathias Soeken, Yinshui Xia, Lun-Yao Wang, Giovanni De Micheli

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Enabling accuracy-aware Quantum compilers using symbolic resource estimation.

Giulia Meuli, Mathias Soeken, Martin Roetteler, Thomas Häner

Proc. ACM Program. Lang., 2020

A Spectral Algorithm for 3-valued Function Equivalence Classification.

D. Michael Miller, Mathias Soeken

J. Multiple Valued Log. Soft Comput., 2020

A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks.

Eleonora Testa, Mathias Soeken, Heinz Riener, Luca G. Amarù, Giovanni De Micheli

IACR Cryptol. ePrint Arch., 2020

Determining the Multiplicative Complexity of Boolean Functions using SAT.

Mathias Soeken

IACR Cryptol. ePrint Arch., 2020

Improved Quantum Circuits for Elliptic Curve Discrete Logarithms.

Thomas Häner, Samuel Jaques, Michael Naehrig, Martin Roetteler, Mathias Soeken

IACR Cryptol. ePrint Arch., 2020

Lowering the T-depth of Quantum Circuits By Reducing the Multiplicative Depth Of Logic Networks.

Thomas Häner, Mathias Soeken

CoRR, 2020

Automatic accuracy management of quantum programs via (near-)symbolic resource estimation.

Giulia Meuli, Mathias Soeken, Martin Roetteler, Thomas Häner

CoRR, 2020

Extending Boolean Methods for Scalable Logic Synthesis.

Eleonora Testa, Luca G. Amarù, Mathias Soeken, Alan Mishchenko, Patrick Vuillod, Pierre-Emmanuel Gaillardon, Giovanni De Micheli

IEEE Access, 2020

Quantum Circuits for Functionally Controlled NOT Gates.

Mathias Soeken, Martin Roetteler

Proceedings of the IEEE International Conference on Quantum Computing and Engineering, 2020

Symbolic Algorithms for Token Swapping.

Bruno Schmitt, Mathias Soeken, Giovanni De Micheli

Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020

Automatic Uniform Quantum State Preparation Using Decision Diagrams.

Fereshte Mozafari, Mathias Soeken, Heinz Riener, Giovanni De Micheli

Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020

Enumerating Optimal Quantum Circuits using Spectral Classification.

Giulia Meuli, Mathias Soeken, Martin Roetteler, Giovanni De Micheli

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic : (Special Session Paper).

Eleonora Testa, Samantha Lubaba Noor, Odysseas Zografos, Mathias Soeken, Francky Catthoor, Azad Naeemi, Giovanni De Micheli

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Exact DAG-Aware Rewriting.

Heinz Riener, Alan Mishchenko, Mathias Soeken

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

LUT-Based Hierarchical Reversible Logic Synthesis.

Mathias Soeken, Martin Roetteler, Nathan Wiebe, Giovanni De Micheli

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Mapping Monotone Boolean Functions into Majority.

Eleonora Testa, Mathias Soeken, Luca Gaetano Amarù, Winston Haaswijk, Giovanni De Micheli

IEEE Trans. Computers, 2019

Logic Synthesis for Established and Emerging Computing.

Eleonora Testa, Mathias Soeken, Luca Gaetano Amarù, Giovanni De Micheli

Proc. IEEE, 2019

ROS: Resource-constrained Oracle Synthesis for Quantum Computers.

Giulia Meuli, Mathias Soeken, Martin Roetteler, Giovanni De Micheli

Proceedings of the Proceedings 16th International Conference on Quantum Physics and Logic, 2019

Using ZDDs in the mapping of quantum circuits.

Mathias Soeken

Proceedings of the Proceedings 16th International Conference on Quantum Physics and Logic, 2019

A Hybrid Method for Spectral Translation Equivalent Boolean Functions.

Mathias Soeken, Eleonora Testa, D. Michael Miller

Proceedings of the IEEE Pacific Rim Conference on Communications, 2019

Logic Optimization of Majority-Inverter Graphs.

Heinz Riener, Eleonora Testa, Winston Haaswijk, Alan Mishchenko, Luca G. Amarù, Giovanni De Micheli, Mathias Soeken

Proceedings of the 22nd Workshop Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2019

Scaling-up ESOP Synthesis for Quantum Compilation.

Bruno Schmitt, Mathias Soeken, Giovanni De Micheli, Alan Mishchenko

Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019

Reversible Pebble Games for Reducing Qubits in Hierarchical Quantum Circuit Synthesis.

Debjyoti Bhattacharjee, Mathias Soeken, Srijit Dutta, Anupam Chattopadhyay, Giovanni De Micheli

Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019

Exact Synthesis of Boolean Functions in Majority-of-Five Forms.

Zhufei Chu, Winston Haaswijk, Mathias Soeken, Yinshui Xia, Lun-Yao Wang, Giovanni De Micheli

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

The Role of Multiplicative Complexity in Compiling Low $T$-count Oracle Circuits.

Giulia Meuli, Mathias Soeken, Earl T. Campbell, Martin Roetteler, Giovanni De Micheli

Proceedings of the International Conference on Computer-Aided Design, 2019

Scalable Boolean Methods in a Modern Synthesis Flow.

Eleonora Testa, Luca G. Amarù, Mathias Soeken, Alan Mishchenko, Patrick Vuillod, Jiong Luo, Christopher Casares, Pierre-Emmanuel Gaillardon, Giovanni De Micheli

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Compiling Permutations for Superconducting QPUs.

Mathias Soeken, Fereshte Mozafari, Bruno Schmitt, Giovanni De Micheli

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

On-the-fly and DAG-aware: Rewriting Boolean Networks with Exact Synthesis.

Heinz Riener, Winston Haaswijk, Alan Mishchenko, Giovanni De Micheli, Mathias Soeken

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Reversible Pebbling Game for Quantum Memory Management.

Giulia Meuli, Mathias Soeken, Martin Roetteler, Nikolaj S. Bjørner, Giovanni De Micheli

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Reducing the Multiplicative Complexity in Logic Networks for Cryptography and Security Applications.

Eleonora Testa, Mathias Soeken, Luca G. Amarù, Giovanni De Micheli

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Scalable Generic Logic Synthesis: One Approach to Rule Them All.

Heinz Riener, Eleonora Testa, Winston Haaswijk, Alan Mishchenko, Luca G. Amarù, Giovanni De Micheli, Mathias Soeken

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Structural rewriting in XOR-majority graphs.

Zhufei Chu, Mathias Soeken, Yinshui Xia, Lun-Yao Wang, Giovanni De Micheli

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018

Logic Synthesis for RRAM-Based In-Memory Computing.

Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Rolf Drechsler

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Behaviour Driven Development for Hardware Design.

Melanie Diepenbeck, Ulrich Kühne, Mathias Soeken, Daniel Große, Rolf Drechsler

IPSJ Trans. Syst. LSI Des. Methodol., 2018

Pairs of majority-decomposing functions.

Mathias Soeken, Eleonora Testa, Alan Mishchenko, Giovanni De Micheli

Inf. Process. Lett., 2018

The complexity of error metrics.

Oliver Keszöcze, Mathias Soeken, Rolf Drechsler

Inf. Process. Lett., 2018

The EPFL Logic Synthesis Libraries.

Mathias Soeken, Heinz Riener, Winston Haaswijk, Giovanni De Micheli

CoRR, 2018

SAT-based {CNOT, T} Quantum Circuit Synthesis.

Giulia Meuli, Mathias Soeken, Giovanni De Micheli

Proceedings of the Reversible Computation - 10th International Conference, 2018

Quantum Circuits for Floating-Point Arithmetic.

Thomas Häner, Mathias Soeken, Martin Roetteler, Krysta M. Svore

Proceedings of the Reversible Computation - 10th International Conference, 2018

Size Optimization of MIGs with an Application to QCA and STMG Technologies.

Heinz Riener, Eleonora Testa, Luca G. Amarù, Mathias Soeken, Giovanni De Micheli

Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018

A Spectral Algorithm for Ternary Function Classification.

D. Michael Miller, Mathias Soeken

Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018

Translating Between the Roots of the Identity in Quantum Computers.

Wouter Castryck, Jeroen Demeyer, Alexis De Vos, Oliver Keszöcze, Mathias Soeken

Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018

Deep Learning for Logic Optimization Algorithms.

Winston Haaswijk, Edo Collins, Benoit Seguin, Mathias Soeken, Frédéric Kaplan, Sabine Süsstrunk, Giovanni De Micheli

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Integrated ESOP Refactoring for Industrial Designs.

Winston Haaswijk, Luca Gaetano Amarù, Patrick Vuillod, Jiong Luo, Mathias Soeken, Giovanni De Micheli

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Majority logic synthesis.

Luca G. Amarù, Eleonora Testa, Miguel Couceiro, Odysseas Zografos, Giovanni De Micheli, Mathias Soeken

Proceedings of the International Conference on Computer-Aided Design, 2018

Practical exact synthesis.

Mathias Soeken, Winston Haaswijk, Eleonora Testa, Alan Mishchenko, Luca Gaetano Amarù, Robert K. Brayton, Giovanni De Micheli

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Programming quantum computers using design automation.

Mathias Soeken, Thomas Häner, Martin Roetteler

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Improvements to boolean resynthesis.

Luca Gaetano Amarù, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Janet Olson, Robert K. Brayton, Giovanni De Micheli

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Canonical computation without canonical representation.

Alan Mishchenko, Robert K. Brayton, Ana Petkovska, Mathias Soeken, Luca G. Amarù, Antun Domic

Proceedings of the 55th Annual Design Automation Conference, 2018

SAT based exact synthesis using DAG topology families.

Winston Haaswijk, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli

Proceedings of the 55th Annual Design Automation Conference, 2018

A best-fit mapping algorithm to facilitate ESOP-decomposition in Clifford+T quantum network synthesis.

Giulia Meuli, Mathias Soeken, Martin Roetteler, Nathan Wiebe, Giovanni De Micheli

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Functional decomposition using majority.

Zhufei Chu, Mathias Soeken, Yinshui Xia, Giovanni De Micheli

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

Exact Synthesis of Majority-Inverter Graphs and Its Applications.

Mathias Soeken, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

metaSMT: focus on your application and not on solver integration.

Heinz Riener, Finn Haedicke, Stefan Frehse, Mathias Soeken, Daniel Große, Rolf Drechsler, Görschwin Fey

Int. J. Softw. Tools Technol. Transf., 2017

Logic Synthesis for Quantum Computing.

Mathias Soeken, Martin Roetteler, Nathan Wiebe, Giovanni De Micheli

CoRR, 2017

A PLiM Computer for the Internet of Things.

Mathias Soeken, Pierre-Emmanuel Gaillardon, Saeideh Shirinzadeh, Rolf Drechsler, Giovanni De Micheli

Computer, 2017

Inverter Propagation and Fan-Out Constraints for Beyond-CMOS Majority-Based Technologies.

Eleonora Testa, Odysseas Zografos, Mathias Soeken, Adrien Vaysset, Mauricio Manfrini, Rudy Lauwereins, Giovanni De Micheli

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Classifying Functions with Exact Synthesis.

Winston Haaswijk, Eleonora Testa, Mathias Soeken, Giovanni De Micheli

Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017

RM3 based logic synthesis (Special session paper).

Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Enabling exact delay synthesis.

Luca Gaetano Amarù, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon, Janet Olson, Robert K. Brayton, Giovanni De Micheli

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains.

Zhufei Chu, Xifan Tang, Mathias Soeken, Ana Petkovska, Grace Zgheib, Luca Gaetano Amarù, Yinshui Xia, Paolo Ienne, Giovanni De Micheli, Pierre-Emmanuel Gaillardon

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

An adaptive prioritized <i>ε</i>-preferred evolutionary algorithm for approximate BDD optimization.

Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, Rolf Drechsler

Proceedings of the Genetic and Evolutionary Computation Conference, 2017

Wave pipelining for majority-based beyond-CMOS technologies.

Odysseas Zografos, A. De Meester, Eleonora Testa, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Luca Gaetano Amarù, Praveen Raghavan, Francky Catthoor, Rudy Lauwereins

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Design automation and design space exploration for quantum computers.

Mathias Soeken, Martin Roetteler, Nathan Wiebe, Giovanni De Micheli

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Busy man's synthesis: Combinational delay optimization with SAT.

Mathias Soeken, Giovanni De Micheli, Alan Mishchenko

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Endurance management for resistive Logic-In-Memory computing architectures.

Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Rolf Drechsler

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Hierarchical Reversible Logic Synthesis Using LUTs.

Mathias Soeken, Martin Roetteler, Nathan Wiebe, Giovanni De Micheli

Proceedings of the 54th Annual Design Automation Conference, 2017

A novel basis for logic rewriting.

Winston Haaswijk, Mathias Soeken, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Multi-level logic benchmarks: An exactness study.

Luca Gaetano Amarù, Mathias Soeken, Winston Haaswijk, Eleonora Testa, Patrick Vuillod, Jiong Luo, Pierre-Emmanuel Gaillardon, Giovanni De Micheli

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

Complexity of reversible circuits and their quantum implementations.

Nabila Abdessaied, Matthew Amy, Rolf Drechsler, Mathias Soeken

Theor. Comput. Sci., 2016

Ancilla-free synthesis of large reversible functions using binary decision diagrams.

Mathias Soeken, Laura Tague, Gerhard W. Dueck, Rolf Drechsler

J. Symb. Comput., 2016

Embedding of Large Boolean Functions for Reversible Logic.

Mathias Soeken, Robert Wille, Oliver Keszöcze, D. Michael Miller, Rolf Drechsler

ACM J. Emerg. Technol. Comput. Syst., 2016

SyReC: A hardware description language for the specification and synthesis of reversible circuits.

Robert Wille, Eleonora Schönborn, Mathias Soeken, Rolf Drechsler

Integr., 2016

Verifying the structure and behavior in UML/OCL models using satisfiability solvers.

Nils Przigoda, Mathias Soeken, Robert Wille, Rolf Drechsler

IET Cyper-Phys. Syst.: Theory & Appl., 2016

Heuristic NPN Classification for Large Functions Using AIGs and LEXSAT.

Mathias Soeken, Alan Mishchenko, Ana Petkovska, Baruch Sterin, Paolo Ienne, Robert K. Brayton, Giovanni De Micheli

Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2016, 2016

A Fast Symbolic Transformation Based Algorithm for Reversible Logic Synthesis.

Mathias Soeken, Gerhard W. Dueck, D. Michael Miller

Proceedings of the Reversible Computation - 8th International Conference, 2016

Enumeration of Reversible Functions and Its Application to Circuit Complexity.

Mathias Soeken, Nabila Abdessaied, Giovanni De Micheli

Proceedings of the Reversible Computation - 8th International Conference, 2016

Inversion optimization in Majority-Inverter Graphs.

Eleonora Testa, Mathias Soeken, Odysseas Zografos, Luca Gaetano Amarù, Praveen Raghavan, Rudy Lauwereins, Pierre-Emmanuel Gaillardon, Giovanni De Micheli

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Symbolic Error Metric Determination for Approximate Computing.

Arun Chandrasekharan, Daniel Große, Mathias Soeken, Rolf Drechsler

Proceedings of the 19th GI/ITG/GMM Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2016

Dynamic NoC buffer allocation for MPSoC timing side channel attack protection.

Johanna Sepúlveda, Daniel Florez, Mathias Soeken, Jean-Philippe Diguet, Guy Gogniat

Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

Notes on Majority Boolean Algebra.

Anupam Chattopadhyay, Luca Gaetano Amarù, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli

Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016

Technology Mapping of Reversible Circuits to Clifford+T Quantum Circuits.

Nabila Abdessaied, Matthew Amy, Mathias Soeken, Rolf Drechsler

Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016

An extension of transformation-based reversible and quantum circuit synthesis.

Mathias Soeken, Gerhard W. Dueck, Md. Mazder Rahman, D. Michael Miller

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Multilevel design understanding: from specification to logic (invited paper).

Sandip Ray, Ian G. Harris, Görschwin Fey, Mathias Soeken

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Fast generation of lexicographic satisfiable assignments: enabling canonicity in SAT-based applications.

Ana Petkovska, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli, Robert K. Brayton, Paolo Ienne

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Approximation-aware rewriting of AIGs for error tolerant applications.

Arun Chandrasekharan, Mathias Soeken, Daniel Große, Rolf Drechsler

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

SAT-Based Combinational and Sequential Dependency Computation.

Mathias Soeken, Pascal Raiola, Baruch Sterin, Bernd Becker, Giovanni De Micheli, Matthias Sauer

Proceedings of the Hardware and Software: Verification and Testing, 2016

Approximate BDD Optimization with Prioritized ε-Preferred Evolutionary Algorithm.

Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, Rolf Drechsler

Proceedings of the Genetic and Evolutionary Computation Conference, 2016

Fast hierarchical NPN classification.

Ana Petkovska, Mathias Soeken, Giovanni De Micheli, Paolo Ienne, Alan Mishchenko

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Equivalence checking using Gröbner bases.

Amr A. R. Sayed-Ahmed, Daniel Große, Mathias Soeken, Rolf Drechsler

Proceedings of the 2016 Formal Methods in Computer-Aided Design, 2016

Multi-objective BDD optimization for RRAM based circuit design.

Saeideh Shirinzadeh, Mathias Soeken, Rolf Drechsler

Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

Optimizing Majority-Inverter Graphs with functional hashing.

Mathias Soeken, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Fast logic synthesis for RRAM-based in-memory computing using Majority-Inverter Graphs.

Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Rolf Drechsler

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Formal verification of integer multipliers by combining Gröbner basis with logic reduction.

Amr A. R. Sayed-Ahmed, Daniel Große, Ulrich Kühne, Mathias Soeken, Rolf Drechsler

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

An MIG-based compiler for programmable logic-in-memory architectures.

Mathias Soeken, Saeideh Shirinzadeh, Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Rolf Drechsler, Giovanni De Micheli

Proceedings of the 53rd Annual Design Automation Conference, 2016

Unlocking efficiency and scalability of reversible logic synthesis using conventional logic synthesis.

Mathias Soeken, Anupam Chattopadhyay

Proceedings of the 53rd Annual Design Automation Conference, 2016

Precise error determination of approximated components in sequential circuits with model checking.

Arun Chandrasekharan, Mathias Soeken, Daniel Große, Rolf Drechsler

Proceedings of the 53rd Annual Design Automation Conference, 2016

BDD minimization for approximate computing.

Mathias Soeken, Daniel Große, Arun Chandrasekharan, Rolf Drechsler

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

Specification-driven model transformation testing.

Esther Guerra, Mathias Soeken

Softw. Syst. Model., 2015

Self-Inverse Functions and Palindromic Circuits.

Mathias Soeken, Michael Kirkedal Thomsen, Gerhard W. Dueck, D. Michael Miller

CoRR, 2015

Reversible circuit rewriting with simulated annealing.

Nabila Abdessaied, Mathias Soeken, Gerhard W. Dueck, Rolf Drechsler

Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Coverage of OCL Operation Specifications and Invariants.

Mathias Soeken, Julia Seiter, Rolf Drechsler

Proceedings of the Tests and Proofs - 9th International Conference, 2015

Ricercar: A Language for Describing and Rewriting Reversible Circuits with Ancillae and Its Permutation Semantics.

Michael Kirkedal Thomsen, Robin Kaarsgaard, Mathias Soeken

Proceedings of the Reversible Computation - 7th International Conference, 2015

Technology Mapping for Single Target Gate Based Circuits Using Boolean Functional Decomposition.

Nabila Abdessaied, Mathias Soeken, Rolf Drechsler

Proceedings of the Reversible Computation - 7th International Conference, 2015

Towards an Automatic Approach for Restricting UML/OCL Invariability Clauses.

Nils Przigoda, Judith Peters, Mathias Soeken, Robert Wille, Rolf Drechsler

Proceedings of the 12th Workshop on Model-Driven Engineering, 2015

Fredkin-Enabled Transformation-Based Reversible Logic Synthesis.

Mathias Soeken, Anupam Chattopadhyay

Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015

Dynamic Template Matching with Mixed-Polarity Toffoli Gates.

Md. Mazder Rahman, Mathias Soeken, Gerhard W. Dueck

Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015

Multi-Objective BDD Optimization with Evolutionary Algorithms.

Saeideh Shirinzadeh, Mathias Soeken, Rolf Drechsler

Proceedings of the Genetic and Evolutionary Computation Conference, 2015

Simulation Graphs for Reverse Engineering.

Mathias Soeken, Baruch Sterin, Rolf Drechsler, Robert K. Brayton

Proceedings of the Formal Methods in Computer-Aided Design, 2015

Requirement Phrasing Assistance Using Automatic Quality Assessment.

Arman Allahyari-Abhari, Mathias Soeken, Rolf Drechsler

Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

Formal Specification Level - Concepts, Methods, and Algorithms.

Mathias Soeken, Rolf Drechsler

Springer, ISBN: 978-3-319-08698-9, 2015

2014

Upper bounds for reversible circuits based on Young subgroups.

Nabila Abdessaied, Mathias Soeken, Michael Kirkedal Thomsen, Rolf Drechsler

Inf. Process. Lett., 2014

Trading off circuit lines and gate costs in the synthesis of reversible logic.

Robert Wille, Mathias Soeken, D. Michael Miller, Rolf Drechsler

Integr., 2014

A framework for reversible circuit complexity.

Mathias Soeken, Nabila Abdessaied, Rolf Drechsler

CoRR, 2014

Behaviour Driven Development for Tests and Verification.

Melanie Diepenbeck, Ulrich Kühne, Mathias Soeken, Rolf Drechsler

Proceedings of the Tests and Proofs - 8th International Conference, 2014

iTac: Aspect Based Sentiment Analysis using Sentiment Trees and Dictionaries.

Fritjof Bornebusch, Glaucia Cancino, Melanie Diepenbeck, Rolf Drechsler, Smith Djomkam, Alvine Nzeungang Fanseu, Maryam Jalali, Marc Michael, Jamal Mohsen, Max Nitze, Christina Plump, Mathias Soeken, Hubert Fred Tchambo, Toni, Henning Ziegler

Proceedings of the 8th International Workshop on Semantic Evaluation, 2014

Self-Verification as the Key Technology for Next Generation Electronic Systems.

Rolf Drechsler, Hoang Minh Le, Mathias Soeken

Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

Mapping NCV Circuits to Optimized Clifford+T Circuits.

D. Michael Miller, Mathias Soeken, Rolf Drechsler

Proceedings of the Reversible Computation - 6th International Conference, 2014

Quantum Circuit Optimization by Hadamard Gate Reduction.

Nabila Abdessaied, Mathias Soeken, Rolf Drechsler

Proceedings of the Reversible Computation - 6th International Conference, 2014

Formale Methoden für Alle.

Mathias Soeken, Max Nitze, Rolf Drechsler

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2014

Requirements Engineering for Cyber-Physical Systems - Challenges in the Context of "Industrie 4.0".

Stefan A. Wiesner, Christian Gorldt, Mathias Soeken, Klaus-Dieter Thoben, Rolf Drechsler

Proceedings of the Advances in Production Management Systems. Innovative and Knowledge-Based Production Management in a Global-Local World, 2014

Automated and quality-driven requirements engineering.

Rolf Drechsler, Mathias Soeken, Robert Wille

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Automating the translation of assertions using natural language processing techniques.

Mathias Soeken, Christopher B. Harris, Nabila Abdessaied, Ian G. Harris, Rolf Drechsler

Proceedings of the 2014 Forum on Specification and Design Languages, 2014

MetaSMT: a unified interface to SMT-LIB2.

Heinz Riener, Mathias Soeken, Clemens Werther, Görschwin Fey, Rolf Drechsler

Proceedings of the 2014 Forum on Specification and Design Languages, 2014

2013

Formal specification level: concepts, methods, and algorithms.

Mathias Soeken

PhD thesis, 2013

Effect of Negative Control Lines on the Exact Synthesis of Reversible Circuits.

Robert Wille, Mathias Soeken, Nils Przigoda, Rolf Drechsler

J. Multiple Valued Log. Soft Comput., 2013

On quantum circuits employing roots of the Pauli matrices.

Mathias Soeken, D. Michael Miller, Rolf Drechsler

CoRR, 2013

White Dots do Matter: Rewriting Reversible Logic Circuits.

Mathias Soeken, Michael Kirkedal Thomsen

Proceedings of the Reversible Computation - 5th International Conference, 2013

Reducing the Depth of Quantum Circuits Using Additional Circuit Lines.

Nabila Abdessaied, Robert Wille, Mathias Soeken, Rolf Drechsler

Proceedings of the Reversible Computation - 5th International Conference, 2013

Generierung von OCL-Ausdrücken aus natürlichsprachlichen Beschreibungen.

Mathias Soeken, Robert Wille, Eugen Kuksa, Rolf Drechsler

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013

Debugging of Reversible Circuits Using pDDs.

Laura Tague, Mathias Soeken, Shin-ichi Minato, Rolf Drechsler

Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013

Exact Template Matching Using Boolean Satisfiability.

Nabila Abdessaied, Mathias Soeken, Robert Wille, Rolf Drechsler

Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013

Grammar-based program generation based on model finding.

Mathias Soeken, Rolf Drechsler

Proceedings of the 8th International Design and Test Symposium, 2013

Towards automatic scenario generation from coverage information.

Melanie Diepenbeck, Mathias Soeken, Daniel Große, Rolf Drechsler

Proceedings of the 8th International Workshop on Automation of Software Test, 2013

Formale Spezifikationsebene.

Mathias Soeken

Proceedings of the Ausgezeichnete Informatikdissertationen 2013, 2013

Text statt C++: Automatisierung des Systementwurfs mit Hilfe natürlicher Sprachverarbeitung.

Rolf Drechsler, Mathias Soeken, Robert Wille

Proceedings of the 43. Jahrestagung der Gesellschaft für Informatik, 2013

Hardware-Software Co-Visualization: Developing systems in the holodeck.

Rolf Drechsler, Mathias Soeken

Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

Towards a generic verification methodology for system models.

Robert Wille, Martin Gogolla, Mathias Soeken, Mirco Kuhlmann, Rolf Drechsler

Proceedings of the Design, Automation and Test in Europe, 2013

Determining relevant model elements for the verification of UML/OCL specifications.

Julia Seiter, Robert Wille, Mathias Soeken, Rolf Drechsler

Proceedings of the Design, Automation and Test in Europe, 2013

Improving the mapping of reversible circuits to quantum circuits using multiple target lines.

Robert Wille, Mathias Soeken, Christian Otterstedt, Rolf Drechsler

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

RevKit: A Toolkit for Reversible Circuit Design.

Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler

J. Multiple Valued Log. Soft Comput., 2012

Assisted Behavior Driven Development Using Natural Language Processing.

Mathias Soeken, Robert Wille, Rolf Drechsler

Proceedings of the Objects, Models, Components, Patterns - 50th International Conference, 2012

Using <i>π</i>DDs in the Design of Reversible Circuits.

Mathias Soeken, Robert Wille, Shin-ichi Minato, Rolf Drechsler

Proceedings of the Reversible Computation, 4th International Workshop, 2012

Property Checking of Quantum Circuits Using Quantum Multiple-Valued Decision Diagrams.

Julia Seiter, Mathias Soeken, Robert Wille, Rolf Drechsler

Proceedings of the Reversible Computation, 4th International Workshop, 2012

Circuit Line Minimization in the HDL-Based Synthesis of Reversible Logic.

Robert Wille, Mathias Soeken, Eleonora Schönborn, Rolf Drechsler

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Exact Synthesis of Toffoli Gate Circuits with Negative Control Lines.

Robert Wille, Mathias Soeken, Nils Przigoda, Rolf Drechsler

Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012

A Synthesis Flow for Sequential Reversible Circuits.

Mathias Soeken, Robert Wille, Christian Otterstedt, Rolf Drechsler

Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012

Optimizing the Mapping of Reversible Circuits to Four-Valued Quantum Gate Circuits.

Mathias Soeken, Zahra Sasanian, Robert Wille, D. Michael Miller, Rolf Drechsler

Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012

Behavior Driven Development for circuit design and verification.

Melanie Diepenbeck, Mathias Soeken, Daniel Große, Rolf Drechsler

Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012

Completeness-Driven Development.

Rolf Drechsler, Melanie Diepenbeck, Daniel Große, Ulrich Kühne, Hoang Minh Le, Julia Seiter, Mathias Soeken, Robert Wille

Proceedings of the Graph Transformations - 6th International Conference, 2012

Formal Specification Level.

Rolf Drechsler, Mathias Soeken, Robert Wille

Proceedings of the Models, Methods, and Tools for Complex Chip Design, 2012

Formal Specification Level: Towards verification-driven design based on natural language processing.

Rolf Drechsler, Mathias Soeken, Robert Wille

Proceedings of the Proceeding of the 2012 Forum on Specification and Design Languages, 2012

Debugging of inconsistent UML/OCL models.

Robert Wille, Mathias Soeken, Rolf Drechsler

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Eliminating invariants in UML/OCL models.

Mathias Soeken, Robert Wille, Rolf Drechsler

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Synthesis of reversible circuits with minimal lines for large functions.

Mathias Soeken, Robert Wille, Christoph Hilken, Nils Przigoda, Rolf Drechsler

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Encoding OCL Data Types for SAT-Based Verification of UML/OCL Models.

Mathias Soeken, Robert Wille, Rolf Drechsler

Proceedings of the Tests and Proofs - 5th International Conference, 2011

RevKit: An Open Source Toolkit for the Design of Reversible Circuits.

Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler

Proceedings of the Reversible Computation - Third International Workshop, 2011

Towards automatic determination of problem bounds for object instantiation in static model verification.

Mathias Soeken, Robert Wille, Rolf Drechsler

Proceedings of the 8th International Workshop on Model-Driven Engineering, 2011

Designing a RISC CPU in Reversible Logic.

Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2011

Towards Automatic Property Generation for the Formal Verification of Bus Bridges.

Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2011

Automatic property generation for the formal verification of bus bridges.

Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler

Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Verifying dynamic aspects of UML models.

Mathias Soeken, Robert Wille, Rolf Drechsler

Proceedings of the Design, Automation and Test in Europe, 2011

2010

Verifying UML/OCL Models Using Boolean Satisfiability.

Mathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2010

Hierarchical synthesis of reversible circuits using positive and negative Davio decomposition.

Mathias Soeken, Robert Wille, Rolf Drechsler

Proceedings of the 5th International Design and Test Workshop, 2010

Window optimization of reversible and quantum circuits.

Mathias Soeken, Robert Wille, Gerhard W. Dueck, Rolf Drechsler

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Reducing the number of lines in reversible circuits.

Robert Wille, Mathias Soeken, Rolf Drechsler

Proceedings of the 47th Design Automation Conference, 2010

2008

Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability.

Robert Wille, Daniel Große, Mathias Soeken, Rolf Drechsler

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008