Mateus Fonseca

Orcid: 0000-0002-8063-2416

According to our database1, Mateus Fonseca authored at least 16 papers between 2005 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2021
Modeling and Evaluating Personas with Software Explainability Requirements.
Proceedings of the Human-Computer Interaction - 7th Iberoamerican Workshop, 2021

2019
IIR Filter Architectures with Truncation Error Feedback for ECG Signal Processing.
Circuits Syst. Signal Process., 2019

Hyperparameter Tuning and its Effects on Cardiac Arrhythmia Prediction.
Proceedings of the 8th Brazilian Conference on Intelligent Systems, 2019

2017
A power-efficient 4-2 Adder Compressor topology.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

Exploiting addition schemes for the improvement of optimized radix-2 and radix-4 fft butterflies.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

Low power sum of absolute differences architecture using novel hybrid adder.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

Using efficient adder compressors with a split-radix butterfly hardware architecture for low-power IoT smart sensors.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

2016
Exploiting adder compressors for power-efficient 2-D approximate DCT realization.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

Exploiting architectural solutions for IIR filter architecture with truncation error feedback.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

Design of optimized radix-2 and radix-4 butterflies from FFT with decimation in time.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

2015
Enhancing a HEVC interpolation filter hardware architecture with efficient adder compressors.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

SATD hardware architecture based on 8×8 Hadamard Transform for HEVC encoder.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

Power efficient 2-D rounded cosine transform with adder compressors for image compression.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

Optimal combination of dedicated multiplication blocks and adder trees schemes for optimized radix-2m array multipliers realization.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

Floating-point adaptive filter architectures for the cancelling of harmonics power line interference.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

2005
Design of a radix-2<sup>m</sup> hybrid array multiplier using carry save adder format.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005


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