Mateus B. Rutzig

Orcid: 0000-0002-2836-2009

According to our database1, Mateus B. Rutzig authored at least 69 papers between 2006 and 2024.

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Bibliography

2024
TARA: Enhancing Real-Time Network Traffic Classification with Hardware Virtual Layers.
Proceedings of the 37th SBC/SBMicro/IEEE Symposium on Integrated Circuits and Systems Design, 2024

Exploiting Virtual Layers and Pruning for FPGA-Based Adaptive Traffic Classification.
Proceedings of the 27th Euromicro Conference on Digital System Design, 2024

2023
Multiprovision: a Design Space Exploration tool for multi-tenant resource provisioning in CPU-GPU environments.
Des. Autom. Embed. Syst., December, 2023

MVSym: Efficient symbiotic exploitation of HLS-kernel multi-versioning for collaborative CPU-FPGA cloud systems.
Integr., November, 2023

Energy-aware fully-adaptive resource provisioning in collaborative CPU-FPGA cloud environments.
J. Parallel Distributed Comput., June, 2023

Dynamic Offloading for Improved Performance and Energy Efficiency in Heterogeneous IoT-Edge-Cloud Continuum.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023

Design Space Exploration for CNN Offloading to FPGAs at the Edge.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023

Resource Provisioning for CPU-FPGA Environments with Adaptive HLS-Versioning and DVFS.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023

Pruning and Early-Exit Co-Optimization for CNN Acceleration on FPGAs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Adaptive Inference on Reconfigurable SmartNICs for Traffic Classification.
Proceedings of the Advanced Information Networking and Applications, 2023

2022
ERIN: Energy-Aware Resource-Provisioning Framework for CPU-FPGA Multitenant Environment.
IEEE Des. Test, 2022

An energy efficient multi-target binary translator for instruction and data level parallelism exploitation.
Des. Autom. Embed. Syst., 2022

SIS-ASTROS: An Integrated Simulation System for the Artillery Saturation Rocket System (ASTROS).
Proceedings of the 12th International Conference on Simulation and Modeling Methodologies, 2022

On the benefits of Collaborative Thread Throttling and HLS-Versioning in CPU-FPGA Environments.
Proceedings of the 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2022

ConfAx: Exploiting Approximate Computing for Configurable FPGA CNN Acceleration at the Edge.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

AdaFlow: A Framework for Adaptive Dataflow CNN Acceleration on FPGAs.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
Synergistically Exploiting CNN Pruning and HLS Versioning for Adaptive Inference on Multi-FPGAs at the Edge.
ACM Trans. Embed. Comput. Syst., 2021

Resource-Aware Collaborative Allocation for CPU-FPGA Cloud Environments.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Dynamic concurrency throttling on NUMA systems and data migration impacts.
Des. Autom. Embed. Syst., 2021

TRIPP: Transparent Resource Provisioning for Multi-Tenant CPU-GPU based Cloud Environments.
Proceedings of the XI Brazilian Symposium on Computing Systems Engineering, 2021

ETCF - Energy-Aware CPU Thread Throttling and Workload Balancing Framework for CPU-FPGA Collaborative Environments.
Proceedings of the XI Brazilian Symposium on Computing Systems Engineering, 2021

FAIR: Fully-Adaptive Framework for Improving Resource Provisioning in Collaborative CPU-FPGA Cloud Environments.
Proceedings of the 33rd IEEE International Symposium on Computer Architecture and High Performance Computing, 2021

Exploiting HLS-Generated Multi-Version Kernels to Improve CPU-FPGA Cloud Systems.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
Data clustering for efficient approximate computing.
Des. Autom. Embed. Syst., 2020

A Management Technique for Concurrent Access to a Reconfigurable Accelerator.
Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020

Unlocking the Full Potential of Heterogeneous Accelerators by Using a Hybrid Multi-Target Binary Translator.
Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020

Maximizing Throughput-per-Joule of a Hybrid Communication Infrastructure Through a Software-Hardware based DVFS Mechanism.
Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020

MCEA: A Resource-Aware Multicore CGRA Architecture for the Edge.
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

2019
A Runtime Power-Aware Phase Predictor for CGRAs.
Proceedings of the 2019 International Conference on ReConFigurable Computing and FPGAs, 2019

Power-Aware Phase Oriented Reconfigurable Architecture.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Boosting SIMD Benefits through a Run-time and Energy Efficient DLP Detection.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Semi-Autonomous Navigation for Virtual Tactical Simulations in the Military Domain.
Proceedings of 8th International Conference on Simulation and Modeling Methodologies, 2018

Runtime Vectorization of Conditional Code and Dynamic Range Loops to ARM NEON Engine.
Proceedings of the VIII Brazilian Symposium on Computing Systems Engineering, 2018

HyHeMPS: A Hybrid Communication Infrastructure for MPSoCs.
Proceedings of the VIII Brazilian Symposium on Computing Systems Engineering, 2018

Improving Software Productivity and Performance Through a Transparent SIMD Execution.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

DIM-VEX: Exploiting Design Time Configurability and Runtime Reconfigurability.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

Exploiting Partial Reconfiguration on a Dynamic Coarse Grained Reconfigurable Architecture.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

2017
A framework to automatically generate heterogeneous organization reconfigurable multiprocessing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Improving EDP in multi-core embedded systems through multidimensional frequency scaling.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
The Impact of Heterogeneity on a Reconfigurable Multicore System.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

A reconfigurable heterogeneous multicore with a homogeneous ISA.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Evaluating Schedulers in a Reconfigurable Multicore Heterogeneous System.
Proceedings of the Applied Reconfigurable Computing - 12th International Symposium, 2016

2015
Adaptive and dynamic reconfigurable multiprocessor system to improve software productivity.
IET Comput. Digit. Tech., 2015

Reducing Storage Costs of Reconfiguration Contexts by Sharing Instruction Memory Cache Blocks.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

2014
A transparent and adaptive reconfigurable system.
Microprocess. Microsystems, 2014

Towards a Dynamic and Reconfigurable Multicore Heterogeneous System.
Proceedings of the 2014 Brazilian Symposium on Computing Systems Engineering, 2014

2013
Multicore Systems on Chip.
Proceedings of the Handbook of Signal Processing Systems, 2013

Towards a multiple-ISA embedded system.
J. Syst. Archit., 2013

A run-time adaptive multiprocessor system.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A transparent and energy aware reconfigurable multiprocessor platform for simultaneous ILP and TLP exploitation.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Mixing static and dynamic strategies for high performance and low area reconfigurable systems.
Int. J. High Perform. Syst. Archit., 2012

Simultaneous reconfiguration of issue-width and instruction cache for a VLIW processor.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

2011
Boosting Parallel Applications Performance on Applying DIM Technique in a Multiprocessing Environment.
Int. J. Reconfigurable Comput., 2011

A reconfigurable fabric supporting full C/C++ input.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

CReAMS: An Embedded Multiprocessor Platform.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

Towards an Adaptable Multiple-ISA Reconfigurable Processor.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

2010
TLP and ILP exploitation through a reconfigurable multiprocessor system.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

A low-energy approach for context memory in reconfigurable systems.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Multi-core Systems on Chip.
Proceedings of the Handbook of Signal Processing Systems, 2010

2009
A low cost and adaptable routing network for reconfigurable systems.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

Dynamically Adapted Low Power ASIPs.
Proceedings of the Reconfigurable Computing: Architectures, 2009

2008
Binary translation process to optimize nanowire arrays usage.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Balancing reconfigurable data path resources according to application requirements.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Reducing interconnection cost in coarse-grained dynamic computing through multistage network.
Proceedings of the FPL 2008, 2008

Transparent Reconfigurable Acceleration for Heterogeneous Embedded Applications.
Proceedings of the Design, Automation and Test in Europe, 2008

Run-time Adaptable Architectures for Heterogeneous Behavior Embedded Systems.
Proceedings of the Reconfigurable Computing: Architectures, 2008

2007
Transparent Dataflow Execution for Embedded Applications.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

2006
Cache performance impacts for stack machines in embedded systems.
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006

Advantages of Java Processors in Cache Performance and Power for Embedded Applications.
Proceedings of the Embedded Computer Systems: Architectures, 2006


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