Mateja Putic

According to our database, Mateja Putic authored at least 7 papers between 2008 and 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2018

Dyhard-DNN: even more DNN acceleration with dynamic hardware reconfiguration.

Mateja Putic, Swagath Venkataramani, Schuyler Eldridge, Alper Buyuktosunoglu, Pradip Bose, Mircea Stan

Proceedings of the 55th Annual Design Automation Conference, 2018

2017

Hierarchical Temporal Memory on the Automata Processor.

Mateja Putic, A. J. Varshneya, Mircea R. Stan

IEEE Micro, 2017

2014

Low Power GPGPU Computation with Imprecise Hardware.

Hang Zhang, Mateja Putic, John C. Lach

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013

Balancing Adder for error tolerant applications.

Matthew Weber, Mateja Putic, Hang Zhang, John C. Lach, Jiawei Huang

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2010

Flexible Circuits and Architectures for Ultralow Power.

Benton H. Calhoun, Joseph F. Ryan, Sudhanshu Khanna, Mateja Putic, John C. Lach

Proc. IEEE, 2010

2009

Panoptic DVS: A fine-grained dynamic voltage scaling framework for energy scalable CMOS design.

Mateja Putic, Liang Di, Benton H. Calhoun, John C. Lach

Proceedings of the 27th International Conference on Computer Design, 2009

2008

Power switch characterization for fine-grained dynamic voltage scaling.

Liang Di, Mateja Putic, John C. Lach, Benton H. Calhoun

Proceedings of the 26th International Conference on Computer Design, 2008