Masumi Saitoh

According to our database, Masumi Saitoh authored at least 11 papers between 2006 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

A Vertical Channel-All-Around FeFET with Thermally Stable Oxide Semiconductor Achieving High ΔIon> 2µA/cell for 3D Stackable 4F² High Speed Memory.

Shoichi Kabuyanagi, Takamasa Hamai, Masayuki Murase, Takeru Maeda, Masumi Saitoh, Shosuke Fujii

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2023

Comprehensive Analysis of Hole-Trapping in SiN Films with a Wide Range of Time Constants Based on Dynamic C-V.

Harumi Seki, Reika Ichihara, Yusuke Higashi, Yasushi Nakasaki, Masumi Saitoh, Masamichi Suzuki

Proceedings of the IEEE International Reliability Physics Symposium, 2023

Novel Operation Scheme for Suppressing Disturb in HfO2-based FeFET Considering Charge- Trapping-Coupled Polarization Dynamics.

Takamasa Hamai, Kunifumi Suzuki, Reika Ichihara, Yusuke Higashi, Yoko Yoshimura, Kiwamu Sakuma, Kensuke Ota, Kota Takahashi, Kazuhiro Matsuo, Shosuke Fujii, Masumi Saitoh

Proceedings of the IEEE International Reliability Physics Symposium, 2023

2020

Breakdown Lifetime Analysis of HfO2-based Ferroelectric Tunnel Junction (FTJ) Memory for In-Memory Reinforcement Learning.

Marina Yamaguchi, Shosuke Fujii, Kensuke Ota, Masumi Saitoh

Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

2019

Ag Ionic Memory Cell Technology for Terabit-Scale High-DensityApplication.

Shosuke Fujii, Reika Ichihara, Takuya Konno, Marina Yamaguchi, Harumi Seki, Hiroki Tanaka, Dandan Zhao, Yoko Yoshimura, Masumi Saitoh, Masato Koyama

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

2018

Hot carrier degradation, TDDB, and 1/f noise in Poly-Si Tri-gate nanowire transistor.

Yoko Yoshimura, Kensuke Ota, Masumi Saitoh

Proceedings of the IEEE International Reliability Physics Symposium, 2018

Impact of specific failure mechanisms on endurance improvement for HfO2-based ferroelectric tunnel junction memory.

Marina Yamaguchi, Shosuke Fujii, Yuuichi Kamimuta, Shoichi Kabuyanagi, Tsunehiro Ino, Yasushi Nakasaki, Riichiro Takaishi, Reika Ichihara, Masumi Saitoh

Proceedings of the IEEE International Reliability Physics Symposium, 2018

Emerging Non-Volatile Memory and Thin-Film Transistor Technologies for Future 3D-LSI.

Masumi Saitoh, Shosuke Fujii, Minoru Oda, Marina Yamaguchi, Shoichi Kabuyanagi, Yoko Yoshimura, Kensuke Ota, Kiwamu Sakuma, Yuuichi Kamimuta

Proceedings of the 48th European Solid-State Device Research Conference, 2018

2016

BSIM4 parameter extraction for tri-gate Si nanowire transistors.

Chika Tanaka, Masumi Saitoh, Kensuke Ota, Takayuki Ishikawa, Toshinori Numata

Microelectron. J., 2016

2015

New layout design methodology for monolithically integrated 3D CMOS logic circuits based on parasitics engineering.

Chika Tanaka, Keiji Ikeda, Masumi Saitoh

Proceedings of the 45th European Solid State Device Research Conference, 2015

2006

Emerging nanoscale silicon devices taking advantage of nanostructure physics.

Toshiro Hiramoto, Masumi Saitoh, Gen Tsutsui

IBM J. Res. Dev., 2006