Masum Hossain
Orcid: 0000-0002-4118-9212
According to our database1,
Masum Hossain
authored at least 41 papers
between 2006 and 2023.
Collaborative distances:
Collaborative distances:
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Bibliography
2023
Differential Edge Modulation Signaling for Low-Energy, High-Speed Wireline Communication.
IEEE Trans. Circuits Syst. I Regul. Pap., 2023
Guest Editorial Introduction to the Special Issue on the 2022 IEEE International Solid-State Circuits Conference (ISSCC).
IEEE J. Solid State Circuits, 2023
2022
Microprocess. Microsystems, March, 2022
IEEE Access, 2022
2021
IEEE Open J. Circuits Syst., 2021
IEEE J. Solid State Circuits, 2021
10-to-112-Gb/s DSP-DAC-Based Transmitter in 7-nm FinFET With Flex Clocking Architecture.
IEEE J. Solid State Circuits, 2021
2020
IEEE J. Solid State Circuits, 2020
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
6.3 A 10-to-112Gb/s DSP-DAC-Based Transmitter with 1.2Vppd Output Swing in 7nm FinFET.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
IEEE J. Solid State Circuits, 2019
Broadband-Tunable Cascaded Vernier Silicon Photonic Microring Filter with Temperature Tracking.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2019
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
A 32Gb/s 2.9pJ/b Transceiver for Sequence-Coded PAM-4 Signalling with 4-to-6dB SNR Gain in 28nm FDSOI CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE J. Solid State Circuits, 2018
IEEE J. Solid State Circuits, 2018
Burst Mode Optical Receiver With 10 ns Lock Time Based on Concurrent DC Offset and Timing Recovery Technique.
JOCN, 2018
Investigation of Wideband Substrate-Integrated Vertically-Polarized Electric Dipole Antenna and Arrays for mm-Wave 5G Mobile Devices.
IEEE Access, 2018
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
Fractional-N DPLL-Based Low-Power Clocking Architecture for 1-14 Gb/s Multi-Standard Transmitter.
IEEE J. Solid State Circuits, 2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
A 82 mW 28 Gb/s PAM-4 digital sequence decoder with built-in error correction in 28nm FDSOI.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
2016
A 35 mW 10 Gb/s ADC-DSP less direct digital sequence detector and equalizer in 65nm CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
Fractional-N DPLL based low power clocking architecture for 1-14 Gb/s multi-standard transmitter.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
2015
IEEE J. Solid State Circuits, 2015
2014
IEEE J. Solid State Circuits, 2014
A 4×40 Gb/s quad-lane CDR with shared frequency tracking and data dependent jitter filtering.
Proceedings of the Symposium on VLSI Circuits, 2014
2012
A 27-Gb/s, 0.41-mW/Gb/s 1-tap predictive decision feedback equalizer in 40-nm low-power CMOS.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
A 6.4/3.2/1.6 Gb/s low power interface with all digital clock multiplier for on-the-fly rate switching.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
2011
IEEE Trans. Circuits Syst. II Express Briefs, 2011
IEEE J. Solid State Circuits, 2011
2010
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
IEEE J. Solid State Circuits, 2010
A 6.8mW 7.4Gb/s clock-forwarded receiver with up to 300MHz jitter tracking in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2009
IEEE J. Solid State Circuits, 2009
2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2006
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006