Masud H. Chowdhury

Microelectron. J., 2022

Investigation of Multiple-valued Logic Technologies for Beyond-binary Era.

[BibT_eX]

[DOI]

Jill Arvindbhai Patel

ACM Comput. Surv., 2022

2021

SecNVM: Power Side-Channel Elimination Using On-Chip Capacitors for Highly Secure Emerging NVM.

[BibT_eX]

[DOI]

Karthikeyan Nagarajan

Mohammad Nasim Imtiaz Khan

Asmit De

Swaroop Ghosh

IEEE Trans. Very Large Scale Integr. Syst., 2021

FinFET based SRAMs in Sub-10nm domain.

[BibT_eX]

[DOI]

Athiya Nizam

Liaquat Ali

Microelectron. J., 2021

A Brief Overview of On-Chip Voltage Regulation in High-Performance and High-Density Integrated Circuits.

[BibT_eX]

[DOI]

IEEE Access, 2021

2020

Design of Ternary Master-Slave D-Flip Flop using MOS-GNRFET.

[BibT_eX]

[DOI]

Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

GNRFET based Ternary Logic - Prospects and Potential Implementation.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

An Implementation of External Capacitor-less Low-DropOut Voltage Regulator in 45nm Technology with Output Voltage Ranging from 0.4V-1.2V.

[BibT_eX]

[DOI]

Proceedings of the 38th IEEE International Conference on Computer Design, 2020

2019

A Low Leakage SRAM Bitcell Design Based on MOS-Type Graphene Nano-Ribbon FET.

[BibT_eX]

[DOI]

Athiya Nizam

Liaquat Ali

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Design of Energy Efficient SRAM Cell Based on Double Gate Schottky-Barrier-Type GNRFET with Minimum Dimer Lines.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018

Reliability and Energy Efficiency of the Tunneling Transistor-Based 6T SRAM Cell in Sub-10 nm Domain.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2018

A New Power Gating Circuit Design Approach Using Double-Gate FDSOI.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2018

Investigation and Optimization of Spiral Inductor Design for On-Chip Buck Converter.

[BibT_eX]

[DOI]

J. Low Power Electron., 2018

Ternary Device using Graphene Memcapacitor for Post Binary Era.

[BibT_eX]

[DOI]

Jill Arvindbhai Patel

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Novel CNTFET and Memristor based Unbalanced Ternary Logic Gate.

[BibT_eX]

[DOI]

Rakesh Vijjapuram

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

A Disturb Free Read Port 8T SRAM Bitcell Circuit Design with Virtual Ground Scheme.

[BibT_eX]

[DOI]

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

An Asynchronous Reconfigurable Switched Capacitor Voltage Regulator.

[BibT_eX]

[DOI]

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Capacitor-less Low-Dropout Regulator (LDO) with Improved PSRR and Enhanced Slew-Rate.

[BibT_eX]

[DOI]

Marouf Khan

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Failure Analysis of the Through Silicon Via in Three-dimensional Integrated Circuit (3D-IC).

[BibT_eX]

[DOI]

Ritesh Kumar Reddy Kuchukulla

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

Analytical Models of High-Speed RLC Interconnect Delay for Complex and Real Poles.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Editorial.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Analysis of device capacitance and subthreshold behavior of Tri-gate SOI FinFET.

[BibT_eX]

[DOI]

Microelectron. J., 2017

Electrical Nonlinearity Emulation Technique for Current-Controlled Memristive Devices.

[BibT_eX]

[DOI]

IEEE Access, 2017

Emerging STT-MRAM circuit and architecture co-design in 45nm technology.

[BibT_eX]

[DOI]

Lohith Kumar Vemula

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Error free sense amplifier circuit design for STT-MRAM nonvolatile memory.

[BibT_eX]

[DOI]

Lohith Kumar Vemula

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Optimization of subthreshold swing for multilayer MoS2 tunnel transistor.

[BibT_eX]

[DOI]

Muhammad Sana Ullah

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Tunneling transistor based 6T SRAM bitcell circuit design in sub-10nm domain.

[BibT_eX]

[DOI]

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Multilayer graphene nanoribbon based BioFET sensor design.

[BibT_eX]

[DOI]

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Impacts of different shapes of through-silicon-via core on 3D IC performance.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Nodal thermal analysis for multi-VT SOFFET based subthreshold circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Noise voltage analysis of spiral inductor for on-chip buck converter design.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

BPSK modulation based exact BER computation for network intra-chip RF interconnect.

[BibT_eX]

[DOI]

Muhammad Sana Ullah

Proceedings of the 29th International Conference on Microelectronics, 2017

2016

Comprehensive doping scheme for MOSFETs in ultra-low-power subthreshold circuits design.

[BibT_eX]

[DOI]

Microelectron. J., 2016

Low voltage Flash memory design based on floating gate SOFFET.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

Innovative device source/drain and channel implantation for MOS transistors in ultra low power subthreshold circuit applications.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

Simple generic memristor emulator for voltage-controlled models.

[BibT_eX]

[DOI]

Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

Detection of biochemical molecules using CM-SOFFET based biosensor.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015

Partially Depleted Silicon-on-Ferroelectric Insulator Field Effect Transistor- Parametrization & Design Optimization for Minimum Subthreshold Swing.

[BibT_eX]

[DOI]

Microelectron. J., 2015

Multilayer Graphene Nanoribbon and Carbon Nanotube Based Floating Gate Transistor for Nonvolatile Flash Memory.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2015

Improved Model for Wire-Length Estimation in Stochastic Wiring Distribution.

[BibT_eX]

[DOI]

Mohamed S. Hefeida

CoRR, 2015

Optimization of ON current in multilayer Molybdenum Disulfide (MoS2) based tunnel field effect transistor.

[BibT_eX]

[DOI]

Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

Subthreshold swing characteristics of multilayer MoS2 tunnel FET.

[BibT_eX]

[DOI]

Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

Analytical analysis of the contact resistance (Rc) of metal-MoS2 interface.

[BibT_eX]

[DOI]

Munem Hossain

Azzedin Es-Saki

Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

New three dimensional doping profile for devices in subthreshold circuit.

[BibT_eX]

[DOI]

Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

Current voltage characteristics of Partially Depleted Silicon on Ferroelectric Insulator Field Effect Transistor (PD-SOFFET).

[BibT_eX]

[DOI]

Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

High-speed graphene based quantum-optical interconnect design.

[BibT_eX]

[DOI]

Ritesh Chowdri

Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

Memristor emulator based on practical current controlled model.

[BibT_eX]

[DOI]

Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

Partially depleted silicon-on-ferroelectric insulator field effect transistor (PD-SOFFET).

[BibT_eX]

[DOI]

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Performance analysis of through silicon via (TSV) and through glass via (TGV) for different materials.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Multilayer molybdenum disulfide (MoS2) based tunnel transistor.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Analysis of radiation effect on the threshold voltage of flash memory device.

[BibT_eX]

[DOI]

Jitendra Koppu

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Analysis of subthreshold swing in multichannel tunneling carbon nanotube field effect transistor (MT-CNTFET).

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Memristor emulator based on single CCII.

[BibT_eX]

[DOI]

Proceedings of the 27th International Conference on Microelectronics, 2015

A new simple emulator circuit for current controlled memristor.

[BibT_eX]

[DOI]

Mohamed E. Fouda

Proceedings of the 2015 IEEE International Conference on Electronics, 2015

A novel memristor emulator based only on an exponential amplifier and CCII+.

[BibT_eX]

[DOI]

Mohamed E. Fouda

Proceedings of the 2015 IEEE International Conference on Electronics, 2015

2014

Multilayer layer graphene nanoribbon flash memory: Analysis of programming and erasing operation.

[BibT_eX]

[DOI]

Md Belayat Hossain

Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

Multichannel Tunneling Carbon Nanotube Field Effect Transistor (MT-CNTFET).

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

Analysis of the current-voltage characteristics of Silicon on Ferroelectric Insulator Field Effect Transistor (SOF-FET).

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

Neural network based classification of stressed speech using nonlinear spectral and cepstral features.

[BibT_eX]

[DOI]

Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

A new real pole delay model for RLC interconnect using second order approximation.

[BibT_eX]

[DOI]

Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

Graphene and CNT based flash memory: Impacts of scaling control and tunnel oxide thickness.

[BibT_eX]

[DOI]

Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

Transistor doping profile optimization for low power subthreshold circuits.

[BibT_eX]

[DOI]

Munem Hossain

Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

Analysis of RLC interconnect delay model using second order approximation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Multilayer graphene nanoribbon floating gate transistor for flash memory.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

Analysis of the properties of ZnO nanoparticle for emerging applications in nanoscale domains.

[BibT_eX]

[DOI]

Md Nahid Hossain

Md. Jahidul Islam

Tajmeri Selina Akhter

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Heat transfer simulations for pulsed laser annealing of silicon thin film.

[BibT_eX]

[DOI]

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Silicon on ferroelectric insulator field effect transistor (SOF-FET) for ultra low power design.

[BibT_eX]

[DOI]

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Implementation of active floating inductor based on second generation current conveyor for on chip voltage regulator.

[BibT_eX]

[DOI]

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Analytical model to estimate the subthreshold swing of SOI FinFET.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Conference on Electronics, 2013

Active on-chip voltage regulator based on second generation current conveyor.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Conference on Electronics, 2013

Thermal aware Graphene based Through Silicon Via design for 3D IC.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012

On-chip voltage regulator without physical inductor.

[BibT_eX]

[DOI]

Md. Tanim Humayun

Proceedings of the 10th IEEE International NEWCAS Conference, 2012

Exploiting negative quantum capacitance of carbon nanotube FETs for low power applications.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011

Fast Waveform Estimation (FWE) for Timing Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

A Hybrid Scheme for On-Chip Voltage Regulation in System-On-a-Chip (SOC).

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

An Innovative Power-Gating Technique for Leakage and Ground Bounce Control in System-on-a-Chip (SOC).

[BibT_eX]

[DOI]

Circuits Syst. Signal Process., 2011

A circuit implementation for dynamic thermal management techniques.

[BibT_eX]

[DOI]

Pritesh Vora

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Spatial- and temporal-reliability aware design for nano-scale VLSI circuits.

[BibT_eX]

[DOI]

Qing Duan

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Addressing crosstalk issue in on-chip carbon nanotube interconnects using negative capacitance.

[BibT_eX]

[DOI]

Md. Khaled Hassan

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010

Analysis of the Impacts of Signal Slew and Skew on the Behavior of Coupled RLC Interconnects for Different Switching Patterns.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2010

Energy efficiency of error control coding in intra-chip RF/wireless interconnect systems.

[BibT_eX]

[DOI]

Microelectron. J., 2010

2009

Investigation and a practical compact network model of thermal stress in integrated circuits.

[BibT_eX]

[DOI]

Shriram Krishnamoorthy

Integr. Comput. Aided Eng., 2009

Crosstalk Avoidance and Error-correction Coding for Coupled RLC Interconnects.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

VSIB: A Sensor Bus Architecture for Smart-Sensor Network.

[BibT_eX]

[DOI]

Proceedings of the CSIE 2009, 2009 WRI World Congress on Computer Science and Information Engineering, March 31, 2009

2008

Compound noise separation in digital circuits using blind source separation.

[BibT_eX]

[DOI]

Microelectron. J., 2008

Noise separation in analog integrated circuits using independent component analysis technique.

[BibT_eX]

[DOI]

Integr. Comput. Aided Eng., 2008

Controlling Ground Bounce Noise in Power Gating Scheme for System-on-a-Chip.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Optimization technique for flip-flop inserted global interconnect.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Full waveform accuracy to estimate delay in coupled digital circuits.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Analysis of the impacts of signal rise/fall time and skew variations in coupled-RLC interconnects.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Time diversity approach for intra-chip RF/wireless interconnect systems.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Innovative power gating for leakage reduction.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Impacts of signal slew and skew variations on delay uncertainty and crosstalk noise in coupled RLC global interconnects.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Fast bus waveform estimation at the presence of coupling noise.

[BibT_eX]

[DOI]

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Improved ber performance in intra-chip rf/wireless interconnect systems.

[BibT_eX]

[DOI]

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

BER performance comparison between CDMA and UWB for RF/wireless interconnect application.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Conference on Electro/Information Technology, 2008

Compact thermal network model: Realization and reduction.

[BibT_eX]

[DOI]

Shriram Krishnamoorthy

Proceedings of the 2008 IEEE International Conference on Electro/Information Technology, 2008

2007

Power Consumption and BER of Flip-Flop Inserted Global Interconnect.

[BibT_eX]

[DOI]

VLSI Design, 2007

Power Consumption Analysis of Flip-flop Based Interconnect Pipelining.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Delay and Clock Skew Variation due to Coupling Capacitance and Inductance.

[BibT_eX]

[DOI]

Noha H. Mahmoud

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Global Interconnect Optimization in the Presence of On-chip Inductance.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Accurate Delay Estimation in the Presence of Coupling Noise using Complete Waveform Accuracy.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on Electronics, 2007

Accurate Analysis of Switching Patterns in High Speed On-chip Global Interconnects.

[BibT_eX]

[DOI]

Sharada Jha

Proceedings of the 14th IEEE International Conference on Electronics, 2007

Multi-Carrier CDMA-Interconnect for Inter- and Intra-ULSI Communications.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on Electronics, 2007

Analysis of Spatial Temperature Distribution in ICs.

[BibT_eX]

[DOI]

Shriram Krishnamoorthy

Proceedings of the 14th IEEE International Conference on Electronics, 2007

Interactive presentation: Analysis of power consumption and BER of flip-flop based interconnect pipelining.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Effects of Coupling Capacitance and Inductance on Delay Uncertainty and Clock Skew.

[BibT_eX]

[DOI]

Noha H. Mahmoud

Proceedings of the 44th Design Automation Conference, 2007

2006

Realistic scalability of noise in dynamic circuits.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2006

Compound noise analysis in digital circuits using blind source separation.

[BibT_eX]

[DOI]

Vivek Nigam

Roland Priemer

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Bit Error Rate Analysis for Flip-flop and Latch Based Interconnect Pipelining.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on Electronics, 2006

Simultaneous Analysis of Capacitive Coupling and Leakage Noise in Nanometer Scale Circuits.

[BibT_eX]

[DOI]

Chuen M. Tan

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Impacts of Inductance on the Figures of Merit to Optimize Global Interconnect.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Separation of Individual Noise Sources from Compound Noise Measurements in Digital Circuits.

[BibT_eX]

[DOI]

Vivek Nigam

Roland Priemer

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Optical Interconnect Technology; Photons Based Signal Communication.

[BibT_eX]

[DOI]

Geetanjali Kshirsagar

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Prospects and Challenges of Handling Power Bus Modeling and Supply Noise in Package-Chip C0-design Approach.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005

Realizable reduction of interconnect circuits including self and mutual inductances.

[BibT_eX]

[DOI]

Chirayu S. Amin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Engineering Over-Clocking: Reliability-Performance Trade-Offs for High-Performance Register Files.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Dependable Systems and Networks (DSN 2005), 28 June, 2005

2004

Possible Noise Failure Modes in Static and Dynamic Circuits.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004

Analysis of coupling noise and it's scalability in dynamic circuits [dynamic logic CMOS ICs].

[BibT_eX]

[DOI]

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003

Analysis of Coupling Noise in Dynamic Circuit.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003

Realizable reduction of RLC circuits using node elimination.

[BibT_eX]

[DOI]

Chirayu S. Amin

Chandramouli V. Kashyap

Byron Krauter

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Realizable RLCK circuit crunching.

[BibT_eX]

[DOI]

Chirayu S. Amin

Proceedings of the 40th Design Automation Conference, 2003

2002

Performance analysis of deep sub micron VLSI circuits in the presence of self and mutual inductance.

[BibT_eX]

[DOI]