Massimo Vatalaro

Orcid: 0000-0001-8689-4073

According to our database¹, Massimo Vatalaro authored at least 8 papers between 2019 and 2025.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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Bibliography

2025

Highly Stable PUFs Based on Stacked Voltage Divider for Near-Zero BER Native Sensitivity to Voltage Variations.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., February, 2025

C4TERO: Configurable Cascaded Carry Chains for High Reliability TERO PUFs on FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., February, 2025

PUF-Based Authentication-Oriented Architecture for Identification Tags.

[BibT_eX]

[DOI]

IEEE Trans. Dependable Secur. Comput., 2025

2024

Exploring the Usage of Fast Carry Chains to Implement Multistage Ring Oscillators on FPGAs: Design and Characterization.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., August, 2024

2023

Experimental analysis of variability in WS<sub>2</sub>-based devices for hardware security.

[BibT_eX]

[DOI]

CoRR, 2023

2022

Static CMOS Physically Unclonable Function Based on 4T Voltage Divider With 0.6%-1.5% Bit Instability at 0.4-1.8 V Operation in 180 nm.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2022

Stability-Area Trade-off in Static CMOS PUF Based on 4T Subthreshold Voltage Divider.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

2019

Making IoT Services Accountable: A Solution Based on Blockchain and Physically Unclonable Functions.

[BibT_eX]

[DOI]

Proceedings of the Internet and Distributed Computing Systems, 2019

Massimo Vatalaro

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