Massimo Rossini

According to our database, Massimo Rossini authored at least 4 papers between 2009 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2016

7.7 A 768Gb 3b/cell 3D-floating-gate NAND flash memory.

Tomoharu Tanaka, Mark Helm, Tommaso Vali, Ramin Ghodsi, Koichi Kawai, Jae-Kwan Park, Shigekazu Yamada, Feng Pan, Yuichi Einaga, Ali Ghalam, Toru Tanzawa, Jason Guo, Takaaki Ichikawa, Erwin Yu, Satoru Tamada, Tetsuji Manabe, Jiro Kishimoto, Yoko Oikawa, Yasuhiro Takashima, Hidehiko Kuge, Midori Morooka, Ali Mohammadzadeh, Jong Kang, Jeff Tsai, Emanuele Sirizotti, Eric Lee, Luyen Vu, Yuxing Liu, Hoon Choi, Kwonsu Cheon, Daesik Song, Daniel Shin, Jung Hee Yun, Michele Piccardi, Kim-Fung Chan, Yogesh Luthra, Dheeraj Srinivasan, Srinivasarao Deshmukh, Kalyan Kavalipurapu, Dan Nguyen, Girolamo Gallo, Sumant Ramprasad, Michelle Luo, Qiang Tang, Michele Incarnati, Agostino Macerola, Luigi Pilolli, Luca De Santis, Massimo Rossini, Violante Moschiano, Giovanni Santin, Bernardino Tronca, Hyunseok Lee, Vipul Patel, Ted Pekny, Aaron Yip, Naveen Prabhu, Purval Sule, Trupti Bemalkhedkar, Kiranmayee Upadhyayula, Camila Jaramillo

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2013

A 128Gb 3b/cell NAND flash design using 20nm planar-cell technology.

Giovanni Naso, L. Botticchio, M. Castelli, C. Cerafogli, M. Cichocki, P. Conenna, Andrea D'Alessandro, Luca De Santis, Domenico Di Cicco, W. Di Francesco, M. L. Gallese, Girolamo Gallo, Michele Incarnati, C. Lattaro, Agostino Macerola, G. G. Marotta, Violante Moschiano, D. Orlandi, F. Paolini, S. Perugini, Luigi Pilolli, P. Pistilli, G. Rizzo, F. Rori, Massimo Rossini, Giovanni Santin, Emanuele Sirizotti, A. Smaniotto, U. Siciliani, Marco Tiburzi, R. Meyer, A. Goda, B. Filipiak, Tommaso Vali, Mark Helm, Ramin Ghodsi

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2010

A 3bit/cell 32Gb NAND flash memory at 34nm with 6MB/s program throughput and with dynamic 2b/cell blocks configuration mode for a program throughput increase up to 13MB/s.

G. G. Marotta, Agostino Macerola, Andrea D'Alessandro, A. Torsi, C. Cerafogli, C. Lattaro, C. Musilli, D. Rivers, Emanuele Sirizotti, F. Paolini, G. Imondi, G. Naso, Giovanni Santin, L. Botticchio, Luca De Santis, Luigi Pilolli, M. L. Gallese, Michele Incarnati, Marco Tiburzi, P. Conenna, S. Perugini, Violante Moschiano, W. Di Francesco, Matt Goldman, Chris Haid, Domenico Di Cicco, D. Orlandi, F. Rori, Massimo Rossini, Tommaso Vali, Ramin Ghodsi, Frank Roohparvar

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009

Reliability improvements in 50 nm MLC NAND flash memory using short voltage programming pulses.

Fernanda Irrera, Ivan Piccoli, Giuseppina Puzzilli, Massimo Rossini, Tommaso Vali

Microelectron. Reliab., 2009