Massimo Poncino

Proceedings of the Design, Automation and Test in Europe, 2011

Partitioned cache architectures for reduced NBTI-induced aging.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

System level techniques to improve reliability in high power microcontrollers for automotive applications.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

2010

Temperature-Insensitive Dual- Vth Synthesis for Nanometer CMOS Technologies Under Inverse Temperature Dependence.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2010

NBTI-Aware Clustered Power Gating.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2010

Thermal-Aware Clock Tree Design to Increase Timing Reliability of Embedded SoCs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Architectural Leakage Power Minimization of Scratchpad Memories by Application-Driven Subbanking.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2010

Dual-Vt assignment policies in ITD-aware synthesis.

[BibT_eX]

[DOI]

Microelectron. J., 2010

A Refinement Methodology for Clock Gating Optimization at Layout Level in Digital Circuits.

[BibT_eX]

[DOI]

J. Low Power Electron., 2010

Dynamic indexing: concurrent leakage and aging optimization for caches.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Analysis of NBTI-induced SNM degradation in power-gated SRAM cells.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Thermal-aware floorplanning exploration for 3D multi-core architectures.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Aging effects of leakage optimizations for caches.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

An integrated thermal estimation framework for industrial embedded platforms.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Post-placement temperature reduction techniques.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

2009

Tag Overflow Buffering: Reducing Total Memory Energy by Reduced-Tag Matching.

[BibT_eX]

[DOI]

Paolo Azzoni

IEEE Trans. Very Large Scale Integr. Syst., 2009

A cosimulation methodology for HW/SW validation and performance estimation.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2009

Design of a Flexible Reactivation Cell for Safe Power-Mode Transition in Power-Gated Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Exploiting Temporal Discharge Current Information to Improve the Efficiency of Clustered Power-Gating.

[BibT_eX]

[DOI]

J. Low Power Electron., 2009

Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

On-chip Thermal Modeling Based on SPICE Simulation.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

Data-Driven Clock Gating for Digital Filters.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

NBTI-aware power gating for concurrent leakage and aging optimization.

[BibT_eX]

[DOI]

Letícia Maria Veiras Bolzani

Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Placement-aware Clustering for Integrated Clock and Power Gating.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Energy-optimal synchronization primitives for single-chip multi-processors.

[BibT_eX]

[DOI]

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Using soft-edge flip-flops to compensate NBTI-induced delay degradation.

[BibT_eX]

[DOI]

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

NBTI-aware sleep transistor design for reliable power-gating.

[BibT_eX]

[DOI]

Letícia Maria Veiras Bolzani

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Enabling concurrent clock and power gating in an industrial design flow.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2008

Thermal-Aware Design Techniques for Nanometer CMOS Circuits.

[BibT_eX]

[DOI]

J. Low Power Electron., 2008

Implementation of a thermal management unit for canceling temperature-dependent clock skew variations.

[BibT_eX]

[DOI]

Integr., 2008

Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

Multiple power-gating domain (multi-VGND) architecture for improved leakage power reduction.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Optimal sleep transistor synthesis under timing and area constraints.

[BibT_eX]

[DOI]

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Energy efficiency bounds of pulse-encoded buses.

[BibT_eX]

[DOI]

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Temperature-insensitive synthesis using multi-vt libraries.

[BibT_eX]

[DOI]

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits.

[BibT_eX]

[DOI]

Letícia Maria Veiras Bolzani

Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

A Scalable Algorithmic Framework for Row-Based Power-Gating.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

2007

Power macromodeling of MPSoC message passing primitives.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2007

Energy-Efficient Multiprocessor Systems-on-Chip for Embedded Computing: Exploring Programming Models and Their Architectural Support.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2007

SystemC co-simulation for core-based embedded systems.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2007

Timing-driven row-based power gating.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Locality-driven architectural cache sub-banking for leakage energy reduction.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Design Exploration of a Thermal Management Unit for Dynamic Control of Temperature-Induced Clock Skew.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

On the energy efficiency of synchronization primitives for shared-memory single-chip multiprocessors.

[BibT_eX]

[DOI]

Olga Golubeva

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology.

[BibT_eX]

[DOI]

Antonio Pullini

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Architectural leakage-aware management of partitioned scratchpad memories.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

Cache coherence tradeoffs in shared-memory MPSoCs.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2006

Low-energy RGB color approximation for digital LCD interfaces.

[BibT_eX]

[DOI]

IEEE Trans. Consumer Electron., 2006

Reducing Conflict Misses by Application-Specific Reconfigurable Indexing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Energy-Efficient Value Based Selective Refresh for Embedded DRAMS.

[BibT_eX]

[DOI]

J. Low Power Electron., 2006

Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Synchronization-driven dynamic speed scaling for MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Low-energy pixel approximation for DVI-based LCD interfaces.

[BibT_eX]

[DOI]

A. Nurrachmat

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Implications of ultra low-voltage devices on design techniques for controlling leakage in NanoCMOS circuits.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

STV-Cache: a leakage energy-efficient architecture for data caches.

[BibT_eX]

[DOI]

Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

ISS-centric modular HW/SW co-simulation.

[BibT_eX]

[DOI]

Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Thermal resilient bounded-skew clock tree optimization methodology.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

Energy-efficient bus encoding for LCD digital display interfaces.

[BibT_eX]

[DOI]

IEEE Trans. Consumer Electron., 2005

Exploiting Cross-Channel Correlation for Energy-Efficient LCD Bus Encoding.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2005

Frame Buffer Energy Optimization by Pixel Prediction.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Energy-Efficient Color Approximation for Digital LCD Interfaces.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Zero clustering: an approach to extend zero compression to instruction caches.

[BibT_eX]

[DOI]

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Exploring the energy efficiency of cache coherence protocols in single-chip multi-processors.

[BibT_eX]

[DOI]

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Exploring Energy/Performance Tradeoffs in Shared Memory MPSoCs: Snoop-Based Cache Coherence vs. Software Solutions.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

Tag Overflow Buffering: An Energy-Efficient Cache Architecture.

[BibT_eX]

[DOI]

Paolo Azzoni

Proceedings of the 2005 Design, 2005

Virtual Hardware Prototyping through Timed Hardware-Software Co-Simulation.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

2004

A Low-Power Encoding Scheme for GigaByte Video Interfaces.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2004

Limited intra-word transition codes: an energy-efficient bus encoding for LCD display interfaces.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

Crosstalk energy reduction by temporal shielding.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Energy-performance tradeoffs for the shared memory in multi-processor systems-on-chip.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Analyzing Power Consumption of Message Passing Primitives in a Single-Chip Multiprocessor.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Software/Network Co-Simulation of Heterogeneous Industrial Networks Architectures.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

DynamoSim: a trace-based dynamically compiled instruction set simulator.

[BibT_eX]

[DOI]

Jianwen Zhu

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Reducing cache misses by application-specific re-configurable indexing.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Cycle-accurate power analysis for multiprocessor systems-on-a-chip.

[BibT_eX]

[DOI]

Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Energy-efficient bus encoding for LCD displays.

[BibT_eX]

[DOI]

Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Synthesis of Partitioned Shared Memory Architectures for Energy-Efficient Multi-Processor SoC.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

Heterogeneous Co-Simulation of Networked Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

Native ISS-SystemC Integration for the Co-Simulation of Multi-Processor SoC.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

Modeling and Analysis of Heterogeneous Industrial Networks Architectures.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

Energy-Efficient Shared Memory Architectures for Multi-Processor Systems-On-Chip.

[BibT_eX]

[DOI]

Proceedings of the Ultra Low-Power Electronics and Design, 2004

2003

Scheduling battery usage in mobile systems.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2003

Energy-aware design of embedded memories: A survey of technologies, architectures, and optimization techniques.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2003

Discharge Current Steering for Battery Lifetime Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2003

SystemC Cosimulation and Emulation of Multiprocessor SoC Designs.

[BibT_eX]

[DOI]

Computer, 2003

A Statistic Power Model for Non-synthetic RTL Operators.

[BibT_eX]

[DOI]

Maurizio Bruno

Proceedings of the Integrated Circuit and System Design, 2003

A SystemC-based Framework for Properties Incompleteness Evaluation.

[BibT_eX]

[DOI]

Proceedings of the Fourth International Workshop on Microprocessor Test and Verification, 2003

Energy-efficient data scrambling on memory-processor interfaces.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Increasing the locality of memory access patterns by low-overhead hardware address relocation.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Combining wire swapping and spacing for low-power deep-submicron buses.

[BibT_eX]

[DOI]

Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

A novel architecture for power maskable arithmetic units.

[BibT_eX]

[DOI]

Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

Improving the Efficiency of Memory Partitioning by Address Clustering.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

Estimation of Bus Performance for a Tuplespace in an Embedded Architecture.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

A timing-accurate modeling and simulation environment for networked embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 40th Design Automation Conference, 2003

Energy-aware design techniques for differential power analysis protection.

[BibT_eX]

[DOI]

Proceedings of the 40th Design Automation Conference, 2003

2002

Minimizing memory access energy in embedded systems by selective instruction compression.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2002

Layout-driven memory synthesis for embedded systems-on-chip.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2002

Discharge current steering for battery lifetime optimization.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Legacy SystemC Co-Simulation of Multi-Processor Systems-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Enhanced clustered voltage scaling for low power.

[BibT_eX]

[DOI]

Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

Wire Placement for Crosstalk Energy Minimization in Address Buses.

[BibT_eX]

[DOI]

Luca Macchiarulo

Proceedings of the 2002 Design, 2002

Memory design techniques for low energy embedded systems.

[BibT_eX]

Kluwer, ISBN: 978-0-7923-7690-3, 2002

2001

Stream synthesis for efficient power simulation based on spectral transforms.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2001

Parameterized RTL power models for soft macros.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2001

Discrete-time battery models for system-level low-power design.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2001

Synthesis of power-managed sequential components based oncomputational kernel extraction.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Low-energy for deep-submicron address buses.

[BibT_eX]

[DOI]

Luca Macchiarulo

Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Current-controlled policies for battery-driven dynamic power management.

[BibT_eX]

[DOI]

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Fast characterization of RTL power macromodels.

[BibT_eX]

[DOI]

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Extending lifetime of portable systems by battery scheduling.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

From Architecture to Layout: Partitioned Memory Synthesis for Embedded Systems-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 38th Design Automation Conference, 2001

2000

Glitch power minimization by selective gate freezing.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2000

Symbolic optimization of interacting controllers based onredundancy identification and removal.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Architectures and synthesis algorithms for power-efficient businterfaces.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

A multilevel engine for fast power simulation of realistic inputstreams.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Increasing Energy Efficiency of Embedded Systems by Application-Specific Memory Hierarchy Generation.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2000

Power Models for Semi-autonomous RTL Macros.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit Design, 2000

RTL Estimation of Steering Logic Power.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit Design, 2000

Power Macromodeling for a High Quality RT-Level Power Estimation.

[BibT_eX]

[DOI]

Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

A recursive algorithm for low-power memory partitioning.

[BibT_eX]

[DOI]

Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

Supporting system-level power exploration for DSP applications.

[BibT_eX]

[DOI]

Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

Regression-based RTL power models for controllers.

[BibT_eX]

[DOI]

Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

A Discrete-Time Battery Model for High-Level Power Estimation.

[BibT_eX]

[DOI]

Proceedings of the 2000 Design, 2000

Synthesis of application-specific memories for power optimization in embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 37th Conference on Design Automation, 2000

1999

Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 1999

Automatic Synthesis of Large Telescopic Units Based on Near-Minimum Timed Supersetting.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1999

Selective instruction compression for memory energy reduction in embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

Parameterized RTL power models for combinational soft macros.

[BibT_eX]

[DOI]

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Regression-Based Macromodeling for Delay Estimation of Behavioral Components.

[BibT_eX]

[DOI]

Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

Clustered Table-Based Macromodels for RTL Power Estimation.

[BibT_eX]

[DOI]

Roberto Corgnati

Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

Region Compression: A New Scheme for Memory Energy Minimization in Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 25th EUROMICRO '99 Conference, 1999

Glitch Power Minimization by Gate Freezing.

[BibT_eX]

[DOI]

Proceedings of the 1999 Design, 1999

Synthesis of Low-Overhead Interfaces for Power-Efficient Communication over Wide Buses.

[BibT_eX]

[DOI]

Proceedings of the 36th Conference on Design Automation, 1999

Kernel-Based Power Optimization of RTL Components: Exact and Approximate Extraction Algorithms.

[BibT_eX]

[DOI]

Proceedings of the 36th Conference on Design Automation, 1999

1998

Power optimization of core-based systems by address bus encoding.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1998

Telescopic units: a new paradigm for performance optimization of VLSI designs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Symbolic algorithms for layout-oriented synthesis of pass transistor logic circuits.

[BibT_eX]

[DOI]

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding.

[BibT_eX]

[DOI]

Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

Timed Supersetting and the Synthesis of Telescopic Units.

[BibT_eX]

[DOI]

Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

Power Estimation of Behavioral Descriptions.

[BibT_eX]

[DOI]

Proceedings of the 1998 Design, 1998

Computational Kernels and their Application to Sequential Power Optimization.

[BibT_eX]

[DOI]

Proceedings of the 35th Conference on Design Automation, 1998

1997

Testing Core-Based Systems: A Symbolic Methodology.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 1997

System-level power optimization of special purpose applications: the beach solution.

[BibT_eX]

[DOI]

Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

Fast power estimation for deterministic input streams.

[BibT_eX]

[DOI]

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Accurate Entropy Calculation for Large Logic Circuits Based on Output Clustering.

[BibT_eX]

[DOI]

Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks.

[BibT_eX]

[DOI]

Proceedings of the European Design and Test Conference, 1997

Telescopic Units: Increasing the Average Throughput of Pipelined Designs by Adaptive Latency Control.

[BibT_eX]

[DOI]

Proceedings of the 34st Conference on Design Automation, 1997

A parallel approach to symbolic traversal based on set partitioning.

[BibT_eX]

Proceedings of the Advances in Hardware Design and Verification, 1997

1996

Automatic state space decomposition for approximate FSM traversal based on circuit analysis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Enhancing FSM Traversal by Temporary Re-Encoding.

[BibT_eX]

[DOI]

Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

Exact Computation of the Entropy of a Logic Circuit.

[BibT_eX]

[DOI]

Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

Test Generation for Networks of Interacting FSMs Using Symbolic Techniques.

[BibT_eX]

[DOI]

Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

BDD-based testability estimation of VHDL designs.

[BibT_eX]

[DOI]

Proceedings of the conference on European design automation, 1996

Symbolic Optimization of FSM Networks Based on Sequential ATPG Techniques.

[BibT_eX]

[DOI]

Proceedings of the 33st Conference on Design Automation, 1996

1995

Using connectivity and spectral methods to characterize the structure of sequential logic circuits.

[BibT_eX]

[DOI]

Microprocess. Microprogramming, 1995

Using symbolic Rademacher-Walsh spectral transforms to evaluate the correlation between Boolean functions.

[BibT_eX]

[DOI]

Proceedings of the 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), 1995

Estimating worst-case power consumption of CMOS circuits modeled as symbolic neural networks.

[BibT_eX]

[DOI]

Proceedings of the 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), 1995

Predicting the functional complexity of combinational circuits by symbolic spectral analysis of Boolean functions.

[BibT_eX]

[DOI]

Mariano Hermida de la Rica

Proceedings of the Proceedings EURO-DAC'95, 1995

Computing the Maximum Power Cycles of a Sequential Circuit.

[BibT_eX]

[DOI]

Proceedings of the 32st Conference on Design Automation, 1995

1994

A Structural Approach to State Space Decomposition for Approximate Reachability Analysis.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

Re-encoding sequential circuits to reduce power dissipation.

[BibT_eX]

[DOI]

Gary D. Hachtel

Abelardo Pardo

Fabio Somenzi

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

An ADD-based algorithm for shortest path back-tracing of large graphs.

[BibT_eX]

[DOI]

Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994

A State Space Decomposition Algorithm for Approximate FSM Traversal.

[BibT_eX]

[DOI]

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993

A study of the resetability of synchronous sequential circuits.

[BibT_eX]

[DOI]

Antonio Lioy

Microprocess. Microprogramming, 1993

On the Resetability of Synchronous Sequential Circuits.

[BibT_eX]

Antonio Lioy