Masoud Shahshahani

According to our database, Masoud Shahshahani authored at least 7 papers between 2016 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

Robust Estimation of FPGA Resources and Performance from CNN Models.

Pingakshya Goswami, Masoud Shahshahani, Dinesh Bhatia

Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022

PPA Based CNN Architecture Explorer.

Masoud Shahshahani, Dinesh Bhatia

Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022

MLSBench: A Benchmark Set for Machine Learning based FPGA HLS Design Flows.

Pingakshya Goswami, Masoud Shahshahani, Dinesh Bhatia

Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022

2021

An Automated Tool for Implementing Deep Neural Networks on FPGA.

Masoud Shahshahani, Mohammad Sabri Abrebekoh, Bahareh Khabbazan, Dinesh Bhatia

Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

Resource and Performance Estimation for CNN Models using Machine Learning.

Masoud Shahshahani, Dinesh Bhatia

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

2020

MLSBench: A Synthesizable Dataset of HLS Designs to Support ML Based Design Flows.

Pingakshya Goswami, Masoud Shahshahani, Dinesh Bhatia

Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

2016

A 16-channel 1.1mm² implantable seizure control SoC with sub-μW/channel consumption and closed-loop stimulation in 0.18µm CMOS.

Mahsa Shoaran, Masoud Shahshahani, Masoud Farivar, Joyel Almajano, Amirhossein Shahshahani, Alexandre Schmid, Anatol Bragin, Yusuf Leblebici, Azita Emami

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016