Masood Qazi

According to our database, Masood Qazi authored at least 13 papers between 2008 and 2014.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2014

A 3.4-pJ FeRAM-Enabled D Flip-Flop in 0.13-µm CMOS for Nonvolatile Processing in Digital Systems.

Masood Qazi, Ajith Amerasekera, Anantha P. Chandrakasan

IEEE J. Solid State Circuits, 2014

2013

Technique for Efficient Evaluation of SRAM Timing Failure.

Masood Qazi, Mehul Tikekar, Lara Dolecek, Devavrat Shah, Anantha P. Chandrakasan

IEEE Trans. Very Large Scale Integr. Syst., 2013

A 3.4pJ FeRAM-enabled D flip-flop in 0.13µm CMOS for nonvolatile processing in digital systems.

Masood Qazi, Ajith Amerasekera, Anantha P. Chandrakasan

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

40.4fJ/bit/mm low-swing on-chip signaling with self-resetting logic repeaters embedded within a mesh NoC in 45nm SOI CMOS.

Sunghyun Park, Masood Qazi, Li-Shiuan Peh, Anantha P. Chandrakasan

Proceedings of the Design, Automation and Test in Europe, 2013

2012

Circuit design for embedded memory in low-power integrated circuits.

Masood Qazi

PhD thesis, 2012

Design of Low-Voltage Digital Building Blocks and ADCs for Energy-Efficient Systems.

Mahmut E. Sinangil, Marcus Yip, Masood Qazi, Rahul Rithe, Joyce Kwong, Anantha P. Chandrakasan

IEEE Trans. Circuits Syst. II Express Briefs, 2012

A Low-Voltage 1 Mb FRAM in 0.13 µm CMOS Featuring Time-to-Digital Sensing for Expanded Operating Margin.

Masood Qazi, Michael Clinton, Steven Bartling, Anantha P. Chandrakasan

IEEE J. Solid State Circuits, 2012

2011

A 512kb 8T SRAM Macro Operating Down to 0.57 V With an AC-Coupled Sense Amplifier and Embedded Data-Retention-Voltage Sensor in 45 nm SOI CMOS.

Masood Qazi, Kevin Stawiasz, Leland Chang, Anantha P. Chandrakasan

IEEE J. Solid State Circuits, 2011

Challenges and Directions for Low-Voltage SRAM.

Masood Qazi, Mahmut E. Sinangil, Anantha P. Chandrakasan

IEEE Des. Test Comput., 2011

A low-voltage 1Mb FeRAM in 0.13μm CMOS featuring time-to-digital sensing for expanded operating margin in scaled CMOS.

Masood Qazi, Michael Clinton, Steven Bartling, Anantha P. Chandrakasan

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010

A 512kb 8T SRAM macro operating down to 0.57V with an AC-coupled sense amplifier and embedded data-retention-voltage sensor in 45nm SOI CMOS.

Masood Qazi, Kevin Stawiasz, Leland Chang, Anantha P. Chandrakasan

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Loop flattening & spherical sampling: Highly efficient model reduction techniques for SRAM yield analysis.

Masood Qazi, Mehul Tikekar, Lara Dolecek, Devavrat Shah, Anantha P. Chandrakasan

Proceedings of the Design, Automation and Test in Europe, 2010

2008

Breaking the simulation barrier: SRAM evaluation through norm minimization.

Lara Dolecek, Masood Qazi, Devavrat Shah, Anantha P. Chandrakasan

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008