Masiar Sistani
According to our database1,
Masiar Sistani
authored at least 4 papers
between 2023 and 2024.
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Bibliography
2024
Ferroelectrically-enhanced Schottky barrier transistors for Logic-in-Memory applications.
CoRR, 2024
Three-Input Combinational Logic Gates based on Reconfigurable Si Field-Effect Transistors.
Proceedings of the Device Research Conference, 2024
Realization and characterization of HZO-based Schottky-Barrier FETs towards Logic-in-Memory applications.
Proceedings of the Device Research Conference, 2024
2023
Bias Spectroscopy of Negative Differential Resistance in Ge Nanowire Cascode Circuits.
Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023