Masiar Sistani

According to our database, Masiar Sistani authored at least 4 papers between 2023 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

Ferroelectrically-enhanced Schottky barrier transistors for Logic-in-Memory applications.

Daniele Nazzari, Lukas Wind, Masiar Sistani, Dominik Mayr, Kihye Kim, Walter M. Weber

CoRR, 2024

Three-Input Combinational Logic Gates based on Reconfigurable Si Field-Effect Transistors.

Lukas Wind, A. Fuchsberger, Masiar Sistani, Walter M. Weber

Proceedings of the Device Research Conference, 2024

Realization and characterization of HZO-based Schottky-Barrier FETs towards Logic-in-Memory applications.

Daniele Nazzari, Lukas Wind, Dominik Mayr, Kihye Kim, Sebastian Lellig, Masiar Sistani, Walter M. Weber

Proceedings of the Device Research Conference, 2024

2023

Bias Spectroscopy of Negative Differential Resistance in Ge Nanowire Cascode Circuits.

Raphael Behrle, Martien I. Den Hertog, Alois Lugstein, Walter M. Weber, Masiar Sistani

Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023