Masazumi Shiochi

According to our database, Masazumi Shiochi authored at least 3 papers between 1995 and 2010.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2010

An Arbitrary Digital Power Noise Generator Using 65 nm CMOS Technology.

Tetsuro Matsuno, Daisuke Fujimoto, Daisuke Kosaka, Naoyuki Hamanishi, Ken Tanabe, Masazumi Shiochi, Makoto Nagata

IEICE Trans. Electron., 2010

2009

A 6-bit arbitrary digital noise emulator in 65nm CMOS technology.

Tetsuro Matsuno, Daisuke Fujimoto, Daisuke Kosaka, Naoyuki Hamanishi, Ken Tanabe, Masazumi Shiochi, Makoto Nagata

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

1995

A 1.6 Gbyte/s data transfer rate 8 Mb embedded DRAM.

Shinji Miyano, Kenji Numata, Katsuhiko Sato, Tomoaki Yabe, Masaharu Wada, Ryo Haga, Motohiro Enkaku, Masazumi Shiochi, Yutaka Kawashima, Masayuki Iwase, Masahisa Ohgata, Junpei Kumagai, Takeshi Yoshida, Masaomi Sakurai, Seiji Kaki, Narutoshi Yanagiya, Hiroshi Shinya, Tohm Fumyama, Paul Hansen, Marc Hannah, Michael Nagy, Anan Nagarajan, Mana Rungsea

IEEE J. Solid State Circuits, November, 1995