Masayuki Sato

Orcid: 0000-0002-4186-5014

Affiliations:
  • Tohoku University, Sendai, Japan


According to our database1, Masayuki Sato authored at least 55 papers between 2010 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
An Efficient Reference Image Sharing Method for the Image-Division Parallel Video Encoding Architecture.
IEICE Trans. Electron., June, 2023

Ising-Based Kernel Clustering.
Algorithms, April, 2023

A dynamic parameter tuning method for SpMM parallel execution.
Concurr. Comput. Pract. Exp., 2023

A Constraint Partition Method for Combinatorial Optimization Problems.
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023

Appropriate Graph-Algorithm Selection for Edge Devices Using Machine Learning.
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023

Multi-scale Loss based Electron Microscopic Image Pair Matching Method.
Proceedings of the International Conference on Machine Learning and Applications, 2023

Performance Evaluation of Tsunami Evacuation Route Planning on Multiple Annealing Machines.
Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023

2022
A Metadata Prefetching Mechanism for Hybrid Memory Architectures.
IEICE Trans. Electron., 2022

Page-Address Coalescing of Vector Gather Instructions for Efficient Address Translation.
Proceedings of the 12th IEEE/ACM Workshop on Irregular Applications: Architectures and Algorithms, 2022

A Partitioned Memory Architecture with Prefetching for Efficient Video Encoders.
Proceedings of the Parallel and Distributed Computing, Applications and Technologies, 2022

An Efficient Reference Image Sharing Method for the Parallel Video Encoding Architecture.
Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2022

2021
Optimizing Load Balance in a Parallel CFD Code for a Large-scale Turbine Simulation on a Vector Supercomputer.
Supercomput. Front. Innov., 2021

Performance and Power Analysis of a Vector Computing System.
Supercomput. Front. Innov., 2021

Efficient Mixed-Precision Tall-and-Skinny Matrix-Matrix Multiplication for GPUs.
Int. J. Netw. Comput., 2021

An External Definition of the One-Hot Constraint and Fast QUBO Generation for High-Performance Combinatorial Clustering.
Int. J. Netw. Comput., 2021

Register Flush-free Runahead Execution for Modern Vector Processors.
Proceedings of the 33rd IEEE International Symposium on Computer Architecture and High Performance Computing, 2021

Optimizations of a Linear Matrix Solver in a Composite Simulation for a Vector Computer.
Proceedings of the 12th International Symposium on Parallel Architectures, 2021

Ising-Based Combinatorial Clustering Using the Kernel Method.
Proceedings of the 14th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2021

A Processor Selection Method based on Execution Time Estimation for Machine Learning Programs.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2021

An Externally-Constrained Ising Clustering Method for Material Informatics.
Proceedings of the Ninth International Symposium on Computing and Networking, 2021

2020
A Dynamic Parameter Tuning Method for High Performance SpMM.
Proceedings of the Parallel and Distributed Computing, Applications and Technologies, 2020

A Deep Reinforcement Learning Based Feature Selector.
Proceedings of the Parallel Architectures, Algorithms and Programming, 2020

Importance of Selecting Data Layouts in the Tsunami Simulation Code.
Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium Workshops, 2020

An Efficient Skinny Matrix-Matrix Multiplication Method by Folding Input Matrices into Tensor Core Operations.
Proceedings of the Eighth International Symposium on Computing and Networking Workshops, 2020

Combinatorial Clustering Based on an Externally-Defined One-Hot Constraint.
Proceedings of the Eighth International Symposium on Computing and Networking, 2020

Energy-efficient Design of an STT-RAM-based Hybrid Cache Architecture.
Proceedings of the 2020 IEEE Symposium in Low-Power and High-Speed Chips, 2020

Optimization of the Himeno Benchmark for SX-Aurora TSUBASA.
Proceedings of the Benchmarking, Measuring, and Optimizing, 2020

2019
A Skewed Multi-banked Cache for Many-core Vector Processors.
Supercomput. Front. Innov., 2019

An Energy-aware Dynamic Data Allocation Mechanism for Many-channel Memory Systems.
Supercomput. Front. Innov., 2019

Optimizing Memory Layout of Hyperplane Ordering for Vector Supercomputer SX-Aurora TSUBASA.
Proceedings of the 2019 IEEE/ACM Workshop on Memory Centric High Performance Computing, 2019

A Hardware Prefetching Mechanism for Vector Gather Instructions.
Proceedings of the 9th IEEE/ACM Workshop on Irregular Applications: Architectures and Algorithms, 2019

An Appropriate Computing System and Its System Parameters Selection Based on Bottleneck Prediction of Applications.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2019

Performance Evaluation of Tsunami Inundation Simulation on SX-Aurora TSUBASA.
Proceedings of the Computational Science - ICCS 2019, 2019

A Layer-Adaptable Cache Hierarchy by a Multiple-layer Bypass Mechanism.
Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2019

Perceptron-based Cache Bypassing for Way-Adaptable Caches.
Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2019

2018
An Adjacent-Line-Merging Writeback Scheme for STT-RAM-Based Last-Level Caches.
IEEE Trans. Multi Scale Comput. Syst., 2018

Performance evaluation of a vector supercomputer SX-aurora TSUBASA.
Proceedings of the International Conference for High Performance Computing, 2018

Search Space Reduction for Parameter Tuning of a Tsunami Simulation on the Intel Knights Landing Processor.
Proceedings of the 12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2018

An energy-aware set-level refreshing mechanism for eDRAM last-level caches.
Proceedings of the 2018 IEEE Symposium in Low-Power and High-Speed Chips, 2018

2017
An Adaptive Demotion Policy for High-Associativity Caches.
Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2017

An application-adaptive data allocation method for multi-channel memory.
Proceedings of the 2017 IEEE Symposium in Low-Power and High-Speed Chips, 2017

An Adjacent-Line-Merging Writeback Scheme for STT-RAM last-level caches.
Proceedings of the 2017 IEEE Symposium in Low-Power and High-Speed Chips, 2017

2016
A cache partitioning mechanism to protect shared data for CMPs.
Proceedings of the 2016 IEEE Symposium in Low-Power and High-Speed Chips, 2016

A power-aware LLC control mechanism for the 3D-stacked memory system.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

2015
FLEXII: A Flexible Insertion Policy for Dynamic Cache Resizing Mechanisms.
IEICE Trans. Electron., 2015

An energy-efficient dynamic memory address mapping mechanism.
Proceedings of the 2015 IEEE Symposium in Low-Power and High-Speed Chips, 2015

2014
MVP-Cache: A Multi-Banked Cache Memory for Energy-Efficient Vector Processing of Multimedia Applications.
IEICE Trans. Inf. Syst., 2014

An energy optimization method for vector processing mechanisms.
Proceedings of the 2014 IEEE Symposium on Low-Power and High-Speed Chips, 2014

On-chip checkpointing with 3D-stacked memories.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014

2013
A Capacity-Aware Thread Scheduling Method Combined with Cache Partitioning to Reduce Inter-Thread Cache Conflicts.
IEICE Trans. Inf. Syst., 2013

A flexible insertion policy for dynamic cache resizing mechanisms.
Proceedings of the 2013 IEEE Symposium on Low-Power and High-Speed Chips, 2013

Vertically integrated processor and memory module design for vector supercomputers.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012
A capacity-efficient insertion policy for dynamic cache resizing mechanisms.
Proceedings of the Computing Frontiers Conference, CF'12, 2012

2010
A voting-based working set assessment scheme for dynamic cache resizing mechanisms.
Proceedings of the 28th International Conference on Computer Design, 2010

A Majority-Based Control Scheme for Way-Adaptable Caches.
Proceedings of the Facing the Multicore-Challenge, 2010


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