Masayuki Ohayashi
According to our database1,
Masayuki Ohayashi
authored at least 3 papers
between 1994 and 1996.
Collaborative distances:
Collaborative distances:
Timeline
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Bibliography
1996
A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry.
IEEE J. Solid State Circuits, 1996
1995
IEEE J. Solid State Circuits, April, 1995
1994
IEEE J. Solid State Circuits, November, 1994