Masayuki Ito

According to our database, Masayuki Ito authored at least 22 papers between 1990 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Architecture Challenges for Heterogeneous Processors in Embedded SoCs.

Masayuki Ito

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

2020

Architecture and Interface for Collaborating with a Group of Agents in an Adversarial Game.

Natsuki Matsunami, Masayuki Ito, Sotaro Karakama

Proceedings of the 9th International Congress on Advanced Applied Informatics, 2020

2018

A Single-Planner Approach to Multi-Modal Humanoid Mobility.

Andrew Dornbush, Karthik Vijayakumar, Sameer Bardapurkar, Fahad Islam, Masayuki Ito, Maxim Likhachev

Proceedings of the 2018 IEEE International Conference on Robotics and Automation, 2018

2017

3.5 A 40nm flash microcontroller with 0.80µs field-oriented-control intelligent motor timer and functional safety system for next-generation EV/HEV.

Hayato Kimura, Hideyuki Noda, Hisaaki Watanabe, Takashi Higuchi, Ryosaku Kobayashi, Masayuki Utsuno, Fumitake Takami, Sugako Otani, Masayuki Ito, Yasuhisa Shimazaki, Naoki Yada, Hiroyuki Kondo

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2013

Compact ROSA for 100-Gb/s (4 × 25 Gb/s) Ethernet with a PLC-based AWG demultiplexer.

Yoshiyuki Doi, Manabu Oguma, Masayuki Ito, Ikuo Ogawa, Toshihide Yoshimatsu, Tetsuichiro Ohno, Eiji Yoshida, Hiroshi Takahashi

Proceedings of the 2013 Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC), 2013

2011

A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core.

Osamu Nishii, Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, Hideo Maejima

IEICE Trans. Electron., 2011

2010

A 45nm 37.3GOPS/W heterogeneous multi-core SoC.

Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, Shigezumi Matsui, Osamu Nishii, Atsushi Hasegawa, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Koichi Terada, Tohru Nojiri, Masashi Satoh, Hiroyuki Mizuno, Kunio Uchiyama, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, Hideo Maejima

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009

Domain Partitioning Technology for Embedded Multicore Processors.

Tohru Nojiri, Yuki Kondo, Naohiko Irie, Masayuki Ito, Hajime Sasaki, Hideo Maejima

IEEE Micro, 2009

A 65 nm Single-Chip Application and Dual-Mode Baseband Processor With Partial Clock Activation and IP-MMU.

Masayuki Ito, Kenichi Nitta, Koji Ohno, Masahito Saigusa, Masaki Nishida, Shinichi Yoshioka, Takahiro Irita, Takao Koike, Tatsuya Kamei, Teruyoshi Komuro, Toshihiro Hattori, Yasuhiro Arai, Yukio Kodama

IEEE J. Solid State Circuits, 2009

Green Multicore-SoC Software-Execution Framework with Timely-Power-Gating Scheme.

Masafumi Onouchi, Keisuke Toyama, Tohru Nojiri, Makoto Sato, Masayoshi Mase, Jun Shirako, Mikiko Sato, Masashi Takada, Masayuki Ito, Hiroyuki Mizuno, Mitaro Namiki, Keiji Kimura, Hironori Kasahara

Proceedings of the ICPP 2009, 2009

A 65nm dual-mode baseband and multimedia application processor SoC with advanced power and memory management.

Tatsuya Kamei, Tetsuhiro Yamada, Takao Koike, Masayuki Ito, Takahiro Irita, Kenichi Nitta, Toshihiro Hattori, Shinichi Yoshioka

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler.

Masayuki Ito, Toshihiro Hattori, Yutaka Yoshida, Kiyoshi Hayase, Tomoichi Hayashi, Osamu Nishii, Yoshihiko Yasu, Atsushi Hasegawa, Masashi Takada, Hiroyuki Mizuno, Kunio Uchiyama, Toshihiko Odaka, Jun Shirako, Masayoshi Mase, Keiji Kimura, Hironori Kasahara

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Bari-bari-II: Jack-up rescue robot with debris opening function.

Hideyuki Tsukagoshi, Ato Kitagawa, Masayuki Ito, Kuniaki Ooe, Ichiro Kiryu, T. Kochiya

Proceedings of the 2008 IEEE International Conference on Robotics and Automation, 2008

2007

A 390MHz Single-Chip Application and Dual-Mode Baseband Processor in 90nm Triple-Vt CMOS.

Masayuki Ito, Toshihiro Hattori, Takahiro Irita, Ken Tatezawa, Fumihito Tanaka, Kenji Hirose, Shinichi Yoshioka, Koji Ohno, Reiko Tsuchihashi, Minoru Sakata, Masayuki Yamamoto, Yuji Aral

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006

A Power Management Scheme Controlling 20 Power Domains for a Single-Chip Mobile Processor.

Toshihiro Hattori, Takahiro Irita, Masayuki Ito, Eiji Yamamoto, Hisashi Kato, Go Sado, Tetsuhiro Yamada, Kunihiko Nishiyama, Hiroshi Yagi, Takao Koike, Yoshihiko Tsuchihashi, Motoki Higashida, Hiroyuki Asano, Izumi Hayashibara, Ken Tatezawa, Yasuhisa Shimazaki, Naozumi Morino, Kenji Hirose, Saneaki Tamaki, Shinichi Yoshioka, Reiko Tsuchihashi, Nobuto Arai, Tomohiro Akiyama, Koji Ohno

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

SH-MobileG1: A single-chip application and dual-mode baseband processor.

Masayuki Ito, Takahiro Irita, Eiji Yamamoto, Kunihiko Nishiyama, Takao Koike, Yoshihiko Tsuchihashi, Hiroyuki Asano, Hiroshi Yagi, Saneaki Tamaki, Ken Tatezawa, Toshihiro Hattori, Shinichi Yoshioka, Koji Ohno

Proceedings of the 2006 IEEE Hot Chips 18 Symposium (HCS), 2006

Hierarchical power distribution and power management scheme for a single chip mobile processor.

Toshihiro Hattori, Takahiro Irita, Masayuki Ito, Eiji Yamamoto, Hisashi Kato, Go Sado, Tetsuhiro Yamada, Kunihiko Nishiyama, Hiroshi Yagi, Takao Koike, Yoshihiko Tsuchihashi, Motoki Higashida, Hiroyuki Asano, Izumi Hayashibara, Ken Tatezawa, Yasuhisa Shimazaki, Naozumi Morino, Yoshihiko Yasu, Tadashi Hoshi, Yujiro Miyairi, Kazumasa Yanagisawa, Kenji Hirose, Saneaki Tamaki, Shinichi Yoshioka, Toshifumi Ishii, Yusuke Kanno, Hiroyuki Mizuno, Tetsuya Yamada, Naohiko Irie, Reiko Tsuchihashi, Nobuto Arai, Tomohiro Akiyama, Koji Ohno

Proceedings of the 43rd Design Automation Conference, 2006

2003

Low Power Multiplication Algorithm for Switching Activity Reduction through Operand Decomposition.

Masayuki Ito, David G. Chinnery, Kurt Keutzer

Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

1997

Efficient Initial Approximation for Multiplicative Division and Square Root by a Multiplication with Operand Modification.

Masayuki Ito, Naofumi Takagi, Shuzo Yajima

IEEE Trans. Computers, 1997

1996

Square Rooting by Iterative Multiply-Additions.

Masayuki Ito, Naofumi Takagi, Shuzo Yajima

Inf. Process. Lett., 1996

1995

Efficient Initial Approximation and Fast Converging Methods for Division and Square Root.

Masayuki Ito, Naofumi Takagi, Shuzo Yajima

Proceedings of the 12th Symposium on Computer Arithmetic (ARITH-12 '95), 1995

1990

Dynamic two-dimensional parallel simulation technique for high-speed fault simulation on a vector processor.

Nagisa Ishiura, Masayuki Ito, Shuzo Yajima

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990