Masayoshi Tachibana

According to our database, Masayoshi Tachibana authored at least 13 papers between 1986 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

Phase difference analysis technique for parametric faults BIST in CMOS analog circuits.

Chatchai Wannaboon, Nattagit Jiteurtragool, Wimol San-Um, Masayoshi Tachibana

IEICE Electron. Express, 2018

Robustification of a One-Dimensional Generic Sigmoidal Chaotic Map with Application of True Random Bit Generation.

Nattagit Jiteurtragool, Masayoshi Tachibana, Wimol San-Um

Entropy, 2018

2017

A simple current-reversible chaotic jerk circuit using inherent tanh(x) of an opamp.

Patinya Ketthong, Wimol San-Um, Banlue Srisuchinwong, Masayoshi Tachibana

IEICE Electron. Express, 2017

2015

An autonomous chaotic oscillator based on hyperbolic tangent nonlinearity.

Chatchai Wannaboon, Masayoshi Tachibana

Proceedings of the 15th International Symposium on Communications and Information Technologies, 2015

True Random Number Generator based on compact chaotic oscillator.

Nattagit Jiteurtragool, Chatchai Wannaboon, Masayoshi Tachibana

Proceedings of the 15th International Symposium on Communications and Information Technologies, 2015

2013

A resistance matching based self-testable current-mode R-2R digital-to-analog converter.

Jun Yuan, Masayoshi Tachibana

IEICE Electron. Express, 2013

2012

A common-mode BIST technique for fully-differential sample-and-hold circuits.

Jun Yuan, Masayoshi Tachibana

IEICE Electron. Express, 2012

2011

A BIST scheme for operational amplifier by checking the stable output of transient response.

Jun Yuan, Masayoshi Tachibana

Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2010

A Fault Signature Characterization Based Analog Circuit Testing Scheme and the Extension of IEEE 1149.4 Standard.

Wimol San-Um, Masayoshi Tachibana

IEICE Trans. Inf. Syst., 2010

A low-jitter supply-regulated charge pump phase-locked loop with built-in test and calibration.

Wimol San-Um, Masayoshi Tachibana

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009

Simultaneous impulse stimulation and response sampling technique for built-in self test of linear analog integrated circuits.

Wimol San-Um, Masayoshi Tachibana

Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

1989

High performance I/O processors for real-time pulse handling.

Masayoshi Tachibana, Yoshihisa Kondo, Yasuo Yamada, Masafumi Takahashi, Haruyuki Tago

Proceedings of the Computer Design: VLSI in Computers and Processors, 1989

1986

A Hardware Maze Router with Application to Interactive Rip-Up and Reroute.

Kei Suzuki, Yusuke Matsunaga, Masayoshi Tachibana, Tatsuo Ohtsuki

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1986