Masatoshi Yamamoto
According to our database1,
Masatoshi Yamamoto
authored at least 4 papers
between 2008 and 2012.
Collaborative distances:
Collaborative distances:
Timeline
2008
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2010
2011
2012
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Bibliography
2012
A VLSI Architecture with Multiple Fast Store-Based Block Parallel Processing for Output Probability and Likelihood Score Computations in HMM-Based Isolated Word Recognition.
IEICE Trans. Electron., 2012
2010
A VLSI Architecture for Output Probability Computations of HMM-Based Recognition Systems with Store-Based Block Parallel Processing.
IEICE Trans. Inf. Syst., 2010
2008
Fast and memory efficient VLSI architecture for output probability computations of HMM-based recognition systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008