Masatoshi Hasegawa

According to our database, Masatoshi Hasegawa authored at least 4 papers between 2001 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2016

3.3 A 25Gb/s multistandard serial link transceiver for 50dB-loss copper cable in 28nm CMOS.

Takayasu Norimatsu, Takashi Kawamoto, Kenji Kogo, Naohiro Kohmu, Fumio Yuki, Norio Nakajima, Takashi Muto, Junya Nasu, Takemasa Komori, Hideki Koba, Tatsunori Usugi, Tomofumi Hokari, Tsuneo Kawamata, Yuichi Ito, Seiichi Umai, Masatoshi Tsuge, Takeo Yamashita, Masatoshi Hasegawa, Keiichi Higeta

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015

3.2 multi-standard 185fsrms 0.3-to-28Gb/s 40dB backplane signal conditioner with adaptive pattern-match 36-Tap DFE and data-rate-adjustment PLL in 28nm CMOS.

Takashi Kawamoto, Takayasu Norimatsu, Kenji Kogo, Fumio Yuki, Norio Nakajima, Masatoshi Tsuge, Tatsunori Usugi, Tomofumi Hokari, Hideki Koba, Takemasa Komori, Junya Nasu, Tsuneo Kawamata, Yuichi Ito, Seiichi Umai, Jun Kumazawa, Hiroaki Kurahashi, Takashi Muto, Takeo Yamashita, Masatoshi Hasegawa, Keiichi Higeta

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2004

Programmable At-Speed Array and Functional BIST for Embedded DRAM LSI.

Masaji Kume, Katsutoshi Uehara, Minoru Itakura, Hideo Sawamoto, Toru Kobayashi, Masatoshi Hasegawa, Hideki Hayashi

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2001

A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory-cell area efficiency of 33%.

Yuji Yokoyama, Nobutaka Itoh, Masatoshi Hasegawa, Masahiro Katayama, Hiroshi Akasaki, Masayuki Kaneda, Toshitsugu Ueda, Yousuke Tanaka, Eiji Yamasaki, Masaya Todokoro, Keinosuke Toriyama, Hiroshi Miki, Masayoshi Yagyu, Kazumasa Takashima, Toru Kobayashi, Syuichi Miyaoka, Nobuo Tamba

IEEE J. Solid State Circuits, 2001