Masato Sakurai
According to our database1,
Masato Sakurai
authored at least 10 papers
between 2002 and 2013.
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Bibliography
2013
Design of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
CMOS Circuits to Measure Timing Jitter Using a Self-Referenced Clock and a Cascaded Time Difference Amplifier With Duty-Cycle Compensation.
IEEE J. Solid State Circuits, 2012
A clock jitter reduction circuit using gated phase blending between self-delayed clock edges.
Proceedings of the Symposium on VLSI Circuits, 2012
A reference-free on-chip timing jitter measurement circuit using self-referenced clock and a cascaded time difference amplifier in 65nm CMOS.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
Analysis of jitter accumulation in interleaved phase frequency detectors for high-accuracy on-chip jitter measurements.
Proceedings of the International SoC Design Conference, 2011
An on-chip timing jitter measurement circuit using a self-referenced clock and a cascaded time difference amplifier with duty-cycle compensation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
2008
Proceedings of the 16th Color and Imaging Conference, 2008
2007
Proceedings of the 15th Color and Imaging Conference, 2007
2004
Proceedings of the Human Vision and Electronic Imaging IX, 2004
2002
Proceedings of the Human Vision and Electronic Imaging VII, 2002