Masato Iwabuchi

According to our database, Masato Iwabuchi authored at least 3 papers between 1994 and 1999.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

1999

A methodology to analyze power, voltage drop and their effects on clock skew/delay in early stages of design.

Masato Iwabuchi, Noboru Sakamoto, Yasushi Sekine, Takashi Omachi

Proceedings of the 1999 International Symposium on Physical Design, 1999

1995

An efficient logic/circuit mixed-mode simulator for analysis of power supply voltage fluctutation.

Mikako Miyama, Goichi Yokomizo, Masato Iwabuchi, Masami Kinoshita

Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994

A 1.5-ns cycle-time 18-kb pseudo-dual-port RAM with 9K logic gates.

Masato Iwabuchi, Masami Usami, Masamori Kashiyama, Takashi Oomori, Shigeharu Murata, Toshiro Hiramoto, Takashi Hashimoto, Yasuhiro Nakajima

IEEE J. Solid State Circuits, April, 1994