Masashi Tawada

Orcid: 0000-0002-1065-3393

According to our database¹, Masashi Tawada authored at least 38 papers between 2011 and 2024.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

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PhD thesis

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On csauthors.net:

Bibliography

2024

An Ising-Machine-Based Solver of Vehicle Routing Problem With Balanced Pick-Up.

[BibT_eX]

[DOI]

IEEE Trans. Consumer Electron., February, 2024

A Novel Classical-Ising Hybrid Annealing Method with QUBO Model Cutting.

[BibT_eX]

[DOI]

Yuta Atobe

Masashi Tawada

Nozomu Togawa

Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024

Optimization of Practical Time-Dependent Vehicle Routing Problem by Ising Machines.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics, 2024

2023

An Efficient Combined Bit-Width Reducing Method for Ising Models.

[BibT_eX]

[DOI]

Yuta Yachi

Masashi Tawada

Nozomu Togawa

IEICE Trans. Inf. Syst., April, 2023

A Bit-Width Reducing Method for Ising Models Guaranteeing the Ground-State Output.

[BibT_eX]

[DOI]

Yuta Yachi

Masashi Tawada

Nozomu Togawa

Proceedings of the 36th IEEE International System-on-Chip Conference, 2023

2022

How to Reduce the Bit-Width of an Ising Model by Adding Auxiliary Spins.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2022

Hybrid Annealing Method Based on subQUBO Model Extraction With Multiple Solution Instances.

[BibT_eX]

[DOI]

Yuta Atobe

Masashi Tawada

Nozomu Togawa

IEEE Trans. Computers, 2022

QUBO Matrix Distorting Method for Consumer Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics, 2022

Efficient Coefficient Bit-Width Reduction Method for Ising Machines.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics, 2022

2021

Mapping Induced Subgraph Isomorphism Problems to Ising Models and Its Evaluations by an Ising Machine.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2021

An Approach to the Vehicle Routing Problem with Balanced Pick-up Using Ising Machines.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on VLSI Design, Automation and Test, 2021

Multi-day Travel Planning Using Ising Machines for Real-world Applications.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Intelligent Transportation Systems Conference, 2021

Reducing Writing Energy Consumption for Non-Volatile Registers Utilizing Frequent Patterns of Sequential Bits on RISC-V Architecture.

[BibT_eX]

[DOI]

Shota Matsuno

Masashi Tawada

Nozomu Togawa

Proceedings of the IEEE International Conference on Consumer Electronics, 2021

2020

Scalable Stochastic Number Duplicators for Accuracy-flexible Arithmetic Circuit Design.

[BibT_eX]

[DOI]

IPSJ Trans. Syst. LSI Des. Methodol., 2020

Designing Stochastic Number Generators Sharing a Random Number Source based on the Randomization Function.

[BibT_eX]

[DOI]

Masashi Tawada

Nozomu Togawa

Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020

Multi-Resolutional Image Format Using Stochastic Numbers and Its Hardware Implementation.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

A New LDPC Code Decoding Method: Expanding the Scope of Ising Machines.

[BibT_eX]

[DOI]

Masashi Tawada

Shu Tanaka

Nozomu Togawa

Proceedings of the 2020 IEEE International Conference on Consumer Electronics (ICCE), 2020

FPGA-based Heterogeneous Solver for Three-Dimensional Routing.

[BibT_eX]

[DOI]

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019

Effectively Partitioned Implementation for Successive-Cancellation Polar Decoder.

[BibT_eX]

[DOI]

Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

Error Correction Coding of Stochastic Numbers Using BER Measurement.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Error Correction System using Stochastic Numbers in Symmetric Channels and Z Channels.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Efficient Ising Model Mapping to Solving Slot Placement Problem.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Consumer Electronics, 2019

Efficient Ising Model Mapping for Induced Subgraph Isomorphism Problems Using Ising Machines.

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE International Conference on Consumer Electronics, 2019

2018

A Relaxed Bit-Write-Reducing and Error-Correcting Code for Non-Volatile Memories.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

Stochastic Number Duplicators Based on Bit Re-Arrangement Using Randomized Bit Streams.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018

2n RRR: Improved Stochastic Number Duplicator Based on Bit Re-Arrangement.

[BibT_eX]

[DOI]

Proceedings of the 2018 New Generation of CAS, 2018

An Effective Stochastic Number Duplicator and Its Evaluations Using Composite Arithmetic Circuits.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

2017

Effective write-reduction method for MLC non-volatile memory.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016

A Bit-Write-Reducing and Error-Correcting Code Generation Method by Clustering ECC Codewords for Non-Volatile Memories.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

2015

ECC-Based Bit-Write Reduction Code Generation for Non-Volatile Memory.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

Code Generation Limiting Maximum and Minimum Hamming Distances for Non-Volatile Memories.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

Bit-Write-Reducing and Error-Correcting Code Generation by Clustering Error-Correcting Codewords for Non-Volatile Memories.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

A bit-write reduction method based on error-correcting codes for non-volatile memories.

[BibT_eX]

[DOI]

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

A write-reducing and error-correcting code generation method for non-volatile memories.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013

A High-Speed Trace-Driven Cache Configuration Simulator for Dual-Core Processor L1 Caches.

[BibT_eX]

[DOI]

Masashi Tawada

Masao Yanagisawa

Nozomu Togawa

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on ASIC, 2013

2011

Exact, Fast and Flexible L1 Cache Configuration Simulation for Embedded Systems.

[BibT_eX]

[DOI]

IPSJ Trans. Syst. LSI Des. Methodol., 2011

Speeding-up exact and fast FIFO-based cache configuration simulation.

[BibT_eX]

[DOI]

Masashi Tawada

Masao Yanagisawa

Nozomu Togawa

IEICE Electron. Express, 2011

Masashi Tawada

Timeline

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On csauthors.net:

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