Masashi Shimanouchi

According to our database, Masashi Shimanouchi authored at least 10 papers between 2001 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2024

Design of 224Gb/s DSP-Based Transceiver in CMOS Technology: Signal Integrity, Architecture, Circuits, and Packaging.

Jihwan Kim, Ariel Cohen, Mike Peng Li, Ajay Balankutty, Sandipan Kundu, Ahmad Khairi, Yoel Krupnik, Yoav Segal, Marco Cusmai, Dror Lazar, Ari Gordon, Noam Familia, Kai Yu, Yutao Liu, Matthew Beach, Priya Wali, Hsinho Wu, Masashi Shimanouchi, Jenny Xiaohong Jiang, Zhiguo Qian, Kemal Aygun, Itamar Levin, Frank O'Mahony

Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

2016

SERDES external loopback test using production parametric-test hardware.

Shalini Arora, Aman Aflaki, Sounil Biswas, Masashi Shimanouchi

Proceedings of the 2016 IEEE International Test Conference, 2016

2013

Theory, model, and applications of non-Gaussian probability density functions for random jitter/noise with non-white power spectral densities.

Daniel Chow, Masashi Shimanouchi, Mike Peng Li

Proceedings of the 2013 IEEE International Test Conference, 2013

Advancements in high-speed link modeling and simulation (An invited paper for CICC 2013).

Mike Peng Li, Masashi Shimanouchi, Hsinho Wu

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2009

New modeling methods for bounded Gaussian jitter (BGJ)/noise (BGN) and their applications in jitter/noise estimation/testing.

Masashi Shimanouchi, Mike P. Li, Daniel Chow

Proceedings of the 2009 IEEE International Test Conference, 2009

2004

Tester Architecture For The Source Synchronous Bus.

A. T. Sivaram, Masashi Shimanouchi, Howard Maassen, Robert Jackson

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Timing Accuracy Enhancement by a New Calibration Scheme for Multi-Gbps ATE.

Masashi Shimanouchi

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003

Periodic Jitter Injection with Direct Time Synthesis by SPPTM ATE for SerDes Jitter Tolerance Test in Production.

Masashi Shimanouchi

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002

New Paradigm for Signal Paths in ATE Pin Electronics are Needed for Serialcom Device Testing.

Masashi Shimanouchi

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2001

An approach to consistent jitter modeling for various jitter aspects and measurement methods.

Masashi Shimanouchi

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001