Masashi Imai
According to our database1,
Masashi Imai
authored at least 54 papers
between 1997 and 2021.
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Bibliography
2021
Proceedings of the 10th IEEE Global Conference on Consumer Electronics, 2021
2020
A simple yet precise capacitance estimation method for on-chip power delivery network towards EMC analysis.
IEICE Electron. Express, 2020
Coarse Grained versus Fine Grained Architectures for Asynchronous Reconfigurable Devices.
Proceedings of the 26th IEEE International Symposium on Asynchronous Circuits and Systems, 2020
2019
Asynchronous Circuit Design and its Applications: Past, Present and Future (NII Shonan Meeting 133).
NII Shonan Meet. Rep., 2019
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
Proceedings of the 25th IEEE International Symposium on Asynchronous Circuits and Systems, 2019
2018
MTJ-based asynchronous circuits for Re-initialization free computing against power failures.
Microelectron. J., 2018
Novel Delay Elements for Bundled-Data Transfer Circuits Based on Two-Phase Handshaking Protocols.
Proceedings of the 24th IEEE International Symposium on Asynchronous Circuits and Systems, 2018
2017
Task Scheduling Based Redundant Task Allocation Method for the Multi-Core Systems with the DTTR Scheme.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
Cooling architectures using thermal sidewalls, interchip plates, and bottom plate for 3D ICs.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017
2016
The synchronous vs. asynchronous NoC routers: an apple-to-apple comparison between synchronous and transition signaling asynchronous designs.
Proceedings of the Tenth IEEE/ACM International Symposium on Networks-on-Chip, 2016
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016
A task allocation method for the DTTR scheme based on task scheduling of fault patterns.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
Proceedings of the 15th International Symposium on Communications and Information Technologies, 2015
A new encoding mechanism for low power inter-chip serial communication in asynchronous circuits.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015
2014
High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs.
IEICE Trans. Inf. Syst., 2014
Multiple-clock multiple-edge-triggered multiple-bit flip-flops for two-phase handshaking asynchronous circuits.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
Energy-and-performance efficient differential domino logic cell libraries for QDI-model-based asynchronous circuits.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
Proceedings of the 2014 International 3D Systems Integration Conference, 2014
2013
Fault Diagnosis and Reconfiguration Method for Network-on-Chip Based Multiple Processor Systems with Restricted Private Memories.
IEICE Trans. Inf. Syst., 2013
2012
Proceedings of the IEEE 18th Pacific Rim International Symposium on Dependable Computing, 2012
Proceedings of the IEEE 18th Pacific Rim International Symposium on Dependable Computing, 2012
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012
2011
Duplicated Execution Method for NoC-based Multiple Processor Systems with Restricted Private Memories.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011
Proceedings of the 17th IEEE International Symposium on Asynchronous Circuits and Systems, 2011
2010
An Efficient Decision Unit for the Pair and Swap Methodology within Chip Multiprocessors.
Proceedings of the 16th IEEE Pacific Rim International Symposium on Dependable Computing, 2010
Pair and swap: An approach to graceful degradation for dependable chip multiprocessors.
Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2010), Chicago, Illinois, USA, June 28, 2010
2009
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
Proceedings of the 27th International Conference on Computer Design, 2009
Fine-Grain Leakage Power Reduction Method for m-out-of-n Encoded Circuits Using Multi-threshold-Voltage Transistors.
Proceedings of the 15th IEEE Symposium on Asynchronous Circuits and Systems, 2009
2008
A design method for 1-out-of-4 encoded low-power self-timed circuits using standard cell libraries.
Proceedings of the 8th International Conference on Application of Concurrency to System Design (ACSD 2008), 2008
2007
Interactive presentation: Task scheduling under performance constraints for reducing the energy consumption of the GALS multi-processor SoC.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
2006
Design Method of High Performance and Low Power Functional Units Considering Delay Variations.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
A Novel Design Method for Asynchronous Bundled-data Transfer Circuits Considering Characteristics of Delay Variations.
Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 2006
2004
Proceedings of the 23rd International Symposium on Reliable Distributed Systems (SRDS 2004), 2004
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004
Evaluation of Delay Variation in Asynchronous Circuits Based on the Scalable-Delay-Insensitive Model.
Proceedings of the 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 2004
2003
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Control Signal Sharing Using Data-Path Delay Information at Control Data Flow Graph Descriptions.
Proceedings of the 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 2003
2002
High Throughput Asynchronous Domino Using Dual output Buffer.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002
Generation and Verification of Timing Constraints for Fine-Grain Pipelined Asynchronous Data-Path Circuits.
Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002
Design and evaluation of high performance microprocessor with reconfigurable on-chip memory.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002
2001
Performance Evaluation of Cascade ALU Architecture for Asynchronous Super-Scalar Processors.
Proceedings of the 7th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2001), 2001
1998
1997
TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997