Masashi Hirano
According to our database1,
Masashi Hirano
authored at least 3 papers
between 1991 and 2000.
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Bibliography
2000
2.44-GFLOPS 300-MHz floating-point vector-processing unit for high-performance 3D graphics computing.
IEEE J. Solid State Circuits, 2000
1991
A 10 ns 54*54 b parallel structured full array multiplier with 0.5 mu m CMOS technology.
IEEE J. Solid State Circuits, April, 1991