Masashi Hirano

According to our database, Masashi Hirano authored at least 3 papers between 1991 and 2000.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2000

Vector Unit Architecture for Emotion Synthesis.

Atsushi Kunimatsu, Nobuhiro Ide, Toshinori Sato, Yukio Endo, Hiroaki Murakami, Takayuki Kamei, Masashi Hirano, Fujio Ishihara, Haruyuki Tago, Masaaki Oka, Akio Ohba, Teiji Yutaka, Toyoshi Okada, Masakazu Suzuoki

IEEE Micro, 2000

2.44-GFLOPS 300-MHz floating-point vector-processing unit for high-performance 3D graphics computing.

Nobuhiro Ide, Masashi Hirano, Yukio Endo, Shin-ichi Yoshioka, Hiroaki Murakami, Atsushi Kunimatsu, Toshinori Sato, Takayuki Kamei, Toyoshi Okada, Masakazu Suzuoki

IEEE J. Solid State Circuits, 2000

1991

A 10 ns 54*54 b parallel structured full array multiplier with 0.5 mu m CMOS technology.

Junji Mori, Masato Nagamatsu, Masashi Hirano, Shigeru Tanaka, Makoto Noda, Yoshiaki Toyoshima, Kazuhiro Hashimoto, Hiroyuki Hayashida, Kenji Maeguchi

IEEE J. Solid State Circuits, April, 1991