Masaru Uesugi

According to our database, Masaru Uesugi authored at least 4 papers between 1989 and 1997.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

1997

On-wafer BIST of a 200-Gb/s failed-bit search for 1-Gb DRAM.

Satoru Tanoi, Yasuhiro Tokunaga, Tetsuya Tanabe, Kazuhiko Takahashi, Atsuhiko Okada, Masahiro Itoh, Yoshiki Nagatomo, Yoshio Ohtsuki, Masaru Uesugi

IEEE J. Solid State Circuits, 1997

1996

A 250-622 MHz deskew and jitter-suppressed clock buffer using two-loop architecture.

Satoru Tanoi, Tetsuya Tanabe, Kazuhiko Takahashi, Sanpei Miyamoto, Masaru Uesugi

IEEE J. Solid State Circuits, 1996

1994

A 32-bank 256-Mb DRAM with cache and TAG.

Satoru Tanoi, Yasuhiro Tanaka, Tetsuya Tanabe, Akio Eta, Toshio Inada, Ryoji Hamazaki, Yoshio Ohtsuki, Masaru Uesugi

IEEE J. Solid State Circuits, November, 1994

1989

A 60-ns 16-Mbit DRAM with a minimized sensing delay caused by bit-line stray capacitance.

Shizuo Chou, Tsuneo Takano, Akio Kita, Fumio Ichikawa, Masaru Uesugi

IEEE J. Solid State Circuits, October, 1989