Masaru Nishimura
Orcid: 0009-0002-1938-1774
According to our database1,
Masaru Nishimura
authored at least 2 papers
in 2024.
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Bibliography
2024
Scalable dual-instruction multiple-data processing on an efficient systolic-array architecture.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2024
Systolic Array-Based Many-Core Processor with Simultaneous Dual-Instruction Issuance.
Proceedings of the 14th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2024