Masaru Kokubo
According to our database1,
Masaru Kokubo
authored at least 23 papers
between 1988 and 2023.
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Bibliography
2023
Modulation Configurations of Phase Locked Loops for High-Speed and High-Precision Wired and Wireless Applications.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., May, 2023
2018
A 50-Gb/s High-Sensitivity (-9.2 dBm) Low-Power (7.9 pJ/bit) Optical Receiver Based on 0.18-µm SiGe BiCMOS Technology.
IEEE J. Solid State Circuits, 2018
2016
A 50.6-Gb/s 7.8-mW/Gb/s -7.4-dBm sensitivity optical receiver based on 0.18-µm SiGe BiCMOS technology.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2016
2015
An electrical and optical concurrent design methodology for enlarging jitter margin of 25.8-Gb/s optical interconnects.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2013
Verification of interference avoidance effect with Adaptive Channel Diversity method based on ISA100.11a standard.
Proceedings of the 2013 IEEE Radio and Wireless Symposium, 2013
2012
100-1000 MHz Programmable Continuous-Time Filter with Auto-Tuning Schemes and Digital Calibration Sequences for HDD Read Channels.
IEICE Trans. Electron., 2012
Adaptive channel diversity method based on ISA100.11a standard for wireless industrial monitoring.
Proceedings of the 2012 IEEE Radio and Wireless Symposium, 2012
2009
100-1000 MHz cutoff frequency, 0-12 dB boost programmable Gm-C filter with digital calibration for HDD read channel.
Proceedings of the 35th European Solid-State Circuits Conference, 2009
A low-jitter 1.5-GHz and large-EMI reduction 10-dBm spread-spectrum clock generator for Serial-ATA.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
IEICE Trans. Commun., 2008
A low-jitter 1.5-GHz and 350-ppm spread-spectrum serial ATA PHY using reference clock with 400-ppm production-frequency tolerance.
Proceedings of the ESSCIRC 2008, 2008
2007
IEEE J. Solid State Circuits, 2007
A Dual-Mode Bluetooth Transceiver with a Two-Point-Modulated Polar-Loop Transmitter and a Frequency-Offset-Compensated Receiver.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
2006
IEICE Trans. Commun., 2006
Spread-Spectrum Clock Generator for Serial ATA with Multi-Bit Sigma-Delta Modulator-Controlled Fractional PLL.
IEICE Trans. Electron., 2006
2005
A GFSK Transmitter Architecture for a Bluetooth RF-IC, Featuring a Variable-Loop-Bandwidth Phase-Locked Loop Modulator.
IEICE Trans. Electron., 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 31st European Solid-State Circuits Conference, 2005
1997
1988
IEEE J. Solid State Circuits, June, 1988