Masao Nakaya

According to our database1, Masao Nakaya authored at least 9 papers between 1993 and 2008.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2008
Special Section on Advanced Technologies in Digital LSIs and Memories.
IEICE Trans. Electron., 2008

2007
Roundtable: Envisioning the Future for Multiprocessor SoC.
IEEE Des. Test Comput., 2007

2000
14-bit 2.2-MS/s sigma-delta ADC's.
IEEE J. Solid State Circuits, 2000

SNDR sensitivity analysis for cascaded ΣΔ modulators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1998
Software pipelining with path selection.
Syst. Comput. Jpn., 1998

1996
Performance Comparison of ILP Machines with Cycle Time Evaluation.
Proceedings of the 23rd Annual International Symposium on Computer Architecture, 1996

1995
Code scheduling on a superscalar processor: SARCH.
Syst. Comput. Jpn., 1995

Unconstrained Speculative Execution with Predicated State Buffering.
Proceedings of the 22nd Annual International Symposium on Computer Architecture, 1995

1993
Speculative Execution and Reducing Branch Penalty in a Parallel Issue Machine.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993


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