Masao Morimoto

According to our database, Masao Morimoto authored at least 13 papers between 2002 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2020

A 29.2 Mb/mm² Ultra High Density SRAM Macro using 7nm FinFET Technology with Dual-Edge Driven Wordline/Bitline and Write/Read-Assist Circuit.

Yoshisato Yokoyama, Miki Tanaka, Koji Tanaka, Masao Morimoto, Makoto Yabuuchi, Yuichiro Ishii, Shinji Tanaka

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

A 7nm Fin-FET 4.04-Mb/mm2 TCAM with Improved Electromigration Reliability Using Far-Side Driving Scheme and Self-Adjust Reference Match-Line Amplifier.

Makoto Yabuuchi, Masao Morimoto, Yasumasa Tsukamoto, Shinji Tanaka

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

2018

12-NM Fin-FET 3.0G-Search/s 80-Bit × 128-Entry Dual-Port Ternary CAM.

Makoto Yabuuchi, Masao Morimoto, Koji Nii, Shinji Tanaka

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

2016

A 5.92-Mb/mm² 28-nm pseudo 2-read/write dual-port SRAM using double pumping circuitry.

Yuichiro Ishii, Makoto Yabuuchi, Yohei Sawada, Masao Morimoto, Yasumasa Tsukamoto, Yuta Yoshida, Ken Shibata, Toshiaki Sano, Shinji Tanaka, Koji Nii

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015

1.8 Mbit/mm² ternary-CAM macro with 484 ps search access time in 16 nm Fin-FET bulk CMOS technology.

Yasumasa Tsukamoto, Masao Morimoto, Makoto Yabuuchi, Miki Tanaka, Koji Nii

Proceedings of the Symposium on VLSI Circuits, 2015

2014

13.3 20nm High-density single-port and dual-port SRAMs with wordline-voltage-adjustment system for read/write assists.

Makoto Yabuuchi, Yasumasa Tsukamoto, Masao Morimoto, Miki Tanaka, Koji Nii

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013

A 0.41 µA Standby Leakage 32 kb Embedded SRAM with Low-Voltage Resume-Standby Utilizing All Digital Current Comparator in 28 nm HKMG CMOS.

Noriaki Maeda, Shigenobu Komatsu, Masao Morimoto, Koji Tanaka, Yasumasa Tsukamoto, Koji Nii, Yasuhisa Shimazaki

IEEE J. Solid State Circuits, 2013

2012

A 0.41µA standby leakage 32Kb embedded SRAM with Low-Voltage resume-standby utilizing all digital current comparator in 28nm HKMG CMOS.

Noriaki Maeda, Shigenobu Komatsu, Masao Morimoto, Yasuhisa Shimazaki

Proceedings of the Symposium on VLSI Circuits, 2012

2009

A 40-nm low-power SRAM with multi-stage replica-bitline technique for reducing timing variation.

Shigenobu Komatsu, Masanao Yamaoka, Masao Morimoto, Noriaki Maeda, Yasuhisa Shimazaki, Kenichi Osada

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2007

Asymmetric Slope Dual Mode Differential Logic Circuit for Compatibility of Low-Power and High-Speed Operations.

Masao Morimoto, Makoto Nagata, Kazuo Taki

IEICE Trans. Electron., 2007

2005

Logic Synthesis Technique for High Speed Differential Dynamic Logic with Asymmetric Slope Transition.

Masao Morimoto, Yoshinori Tanaka, Makoto Nagata, Kazuo Taki

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

High-Speed Digital Circuit Design Using Differential Logic with Asymmetric Signal Transition.

Masao Morimoto, Makoto Nagata, Kazuo Taki

IEICE Trans. Electron., 2005

2002

An ultra low power, realtime MPEG2 MP@HL motion estimation processor core with SIMD datapath architecture optimized for gradient descent search algorithm.

Masayuki Miyama, Osamu Tooyama, N. Takamatsu, T. Kodake, K. Nakamura, A. Kato, Junichi Miyakoshi, K. Hashimoto, Shigenobu Komatsu, M. Yagi, Masao Morimoto, Kazuo Taki, Masahiko Yoshimoto

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002