Masao Iriguchi
According to our database1,
Masao Iriguchi
authored at least 4 papers
between 2012 and 2015.
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Bibliography
2015
A 60 dB SNDR 35 MS/s SAR ADC With Comparator-Noise-Based Stochastic Residue Estimation.
IEEE J. Solid State Circuits, 2015
2014
A complementary dynamic residue amplifier for a 67 dB SNDR 1.36 mW 170 MS/s pipelined SAR ADC.
Proceedings of the ESSCIRC 2014, 2014
2012
A 1.7 mW 11b 250 MS/s 2-Times Interleaved Fully Dynamic Pipelined SAR ADC in 40 nm Digital CMOS.
IEEE J. Solid State Circuits, 2012
A 1.7mW 11b 250MS/s 2× interleaved fully dynamic pipelined SAR ADC in 40nm digital CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012