Masao Hotta

According to our database1, Masao Hotta authored at least 34 papers between 1989 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2001, "For contributions to the development of low-power video-frequency Analog to Digital converters for mixed-signal system Large Scale Integrated circuits.".

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Thermal Noise Analysis of Ring Amplifier in Cyclic Analog-to-Digital Converter.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., May, 2023

2021
A Low-voltage Non-binary Cyclic ADC using Fully Differential Ring Amplifier.
Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2021

A 0.7V 14bit Hybrid ADC in 65nm SOTB CMOS.
Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2021

A 0.8V 14bit 294kSPS non-binary cyclic ADC in 65nm SOTB CMOS technology.
Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2021

2019
A 0.8V 14bit 62.5kSPS non-binary cyclic ADC using SOTB CMOS technology.
Proceedings of the 2019 International Symposium on Intelligent Signal Processing and Communication Systems, 2019

2017
A 12-bit 1.25MS/s Area-Efficient Radix-Value Self-Estimated Non-Binary Cyclic ADC with Relaxed Requirements on Analog Components.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Experimental results of reconfigurable non-binary cyclic ADC.
Proceedings of the 2017 International Symposium on Intelligent Signal Processing and Communication Systems, 2017

The design of a 14-bit 400kSPS non-binary pipeline cyclic ADC.
Proceedings of the 2017 International Symposium on Intelligent Signal Processing and Communication Systems, 2017

A 12-Bit 3.3MS/S pipeline cyclic ADC with correlated level shifting technique.
Proceedings of the 2017 International Symposium on Intelligent Signal Processing and Communication Systems, 2017

A 14bit 80kSPS non-binary cyclic ADC without high accuracy analog components.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Non-binary cyclic ADC with correlated level shifting technique.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2015
A 10-bit 10Ms/s pipeline cyclic ADC based on β-expansion.
Proceedings of the 2015 International Symposium on Intelligent Signal Processing and Communication Systems, 2015

2014
Experimental Implementation of Non-binary Cyclic ADCs with Radix Value Estimation Algorithm.
IEICE Trans. Electron., 2014

An area-efficient 12-bit 1.25MS/s radix-value self-estimated non-binary ADC with relaxed requirements on analog components.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
Robust Cyclic ADC Architecture Based on β-Expansion.
IEICE Trans. Electron., 2013

Non-binary Pipeline Analog-to-Digital Converter Based on β-Expansion.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Rigorous analysis of quantization error of an A/D converter based on β-map.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2010
A Cascaded Folding ADC Based on Fast-Settling 3-Degree Folders with Enhanced Reset Technique.
IEICE Trans. Electron., 2010

SAR ADC Algorithm with Redundancy and Digital Error Correction.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Non-binary SAR ADC with digital error correction for low power applications.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009
A Time-to-Digital Converter with small circuitry.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
SAR ADC algorithm with redundancy.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
A Second-Order Multibit Complex Bandpass DeltaSigmaAD Modulator with I, Q Dynamic Matching and DWA Algorithm.
IEICE Trans. Electron., 2007

A 2.8-V Multibit Complex Bandpass Delta-Sigma-AD Modulator in 0.18µm CMOS.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
High-Speed Continuous-Time Subsampling Bandpass DeltaSigmaAD Modulator Architecture Employing Radio Frequency DAC.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Complex Bandpass DeltaSigmaAD Modulator Architecture without I, Q-Path Crossing Layout.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Key Technologies for Miniaturization and Power Reduction of Analog-to-Digital Converters for Video Use.
IEICE Trans. Electron., 2006

2005
An 11-bit 160-MS/s 1.35-V 10-mW D/A converter using automated device sizing system.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2002
Analog intellectual property: now? Or never?
Proceedings of the 39th Design Automation Conference, 2002

1996
Correction to "Voltage-Comparator-Based Measurement of Equivalentiy Samlpled Substrate Noise Wavefor.
IEEE J. Solid State Circuits, 1996

Voltage-comparator-based measurement of equivalently sampled substrate noise waveforms in mixed-signal integrated circuits.
IEEE J. Solid State Circuits, 1996

1995
Measurement of digital noise in mixed-signal integrated circuits.
IEEE J. Solid State Circuits, February, 1995

1992
Maximum-likelihood estimation of current-dipole parameters for data obtained using multichannel magnetometer.
IEEE Trans. Biomed. Eng., 1992

1989
A 10-bit 20-MHz two-step parallel A/D converter with internal S/H.
IEEE J. Solid State Circuits, February, 1989


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