Masanori Shirahama
According to our database1,
Masanori Shirahama
authored at least 3 papers
between 2000 and 2007.
Collaborative distances:
Collaborative distances:
Timeline
2000
2001
2002
2003
2004
2005
2006
2007
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1
2
1
1
1
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2007
A PND (PMOS-NMOS-Depletion MOS) Type Single Poly Gate Non-Volatile Memory Cell Design with a Differential Cell Architecture in a Pure CMOS Logic Process for a System LSI.
IEICE Trans. Electron., 2007
2005
A 400-MHz random-cycle dual-port interleaved DRAM (D<sup>2</sup>RAM) with standard CMOS Process.
IEEE J. Solid State Circuits, 2005
2000
An 8-ns random cycle embedded RAM macro with dual-port interleaved DRAM architecture (D<sup>2</sup>/RAM).
IEEE J. Solid State Circuits, 2000